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| author | azidar | 2016-01-16 15:24:50 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 15:24:50 -0800 |
| commit | 9dcb5684957e684174d97a45f80d1cfad887a741 (patch) | |
| tree | 1c8b53f66bb59cc39d2931910459470f0495c71a /test/passes/infer-types | |
| parent | ed20e7c6c77543756e1ebc7bc1e6ae7d10911f0a (diff) | |
| parent | c4271d9e428bba7b447ed6d18fb11729d2b61b22 (diff) | |
Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-mem
Diffstat (limited to 'test/passes/infer-types')
| -rw-r--r-- | test/passes/infer-types/primops.fir | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 102a94ae..d2a09367 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -1,4 +1,6 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s +; XFAIL: * +; TODO Talk to Andrew about bit operations (and, or, etc.) on SInts ;CHECK: Infer Types circuit top : |