diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/expand-whens/reg-dwoc.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/expand-whens/reg-dwoc.fir')
| -rw-r--r-- | test/passes/expand-whens/reg-dwoc.fir | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir index 60bd43a8..002f34a5 100644 --- a/test/passes/expand-whens/reg-dwoc.fir +++ b/test/passes/expand-whens/reg-dwoc.fir @@ -4,11 +4,11 @@ circuit top : input clk : Clock input reset : UInt<1> wire p : UInt - p := UInt(1) + p <= UInt(1) reg r : UInt,clk,reset when p : - onreset r := UInt(1) - r := UInt(2) + onreset r <= UInt(1) + r <= UInt(2) ; CHECK: Expand Whens @@ -16,8 +16,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h1") -; CHECK: when p : r := mux(reset, UInt("h1"), UInt("h2")) +; CHECK: p <= UInt("h1") +; CHECK: when p : r <= mux(reset, UInt("h1"), UInt("h2")) ; CHECK: Finished Expand Whens |