diff options
| author | azidar | 2016-01-31 12:59:31 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:06 -0800 |
| commit | e985d47312458459e9ebe42fe99b5a063c08e637 (patch) | |
| tree | d726c711e86d6e948a220a568dcae0a997629d18 /test/passes/const-prop | |
| parent | 2bd423fa061fb3e0973fa83e98f2877fd4616746 (diff) | |
Changed stanza output of UInt/SInt to include widths. Made tests match accordingly
Diffstat (limited to 'test/passes/const-prop')
| -rw-r--r-- | test/passes/const-prop/bits.fir | 2 | ||||
| -rw-r--r-- | test/passes/const-prop/rsh.fir | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/const-prop/bits.fir b/test/passes/const-prop/bits.fir index 78c450a9..74aa19de 100644 --- a/test/passes/const-prop/bits.fir +++ b/test/passes/const-prop/bits.fir @@ -1,7 +1,7 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s ;CHECK: Constant Propagation -;CHECK: node x = UInt("h7") +;CHECK: node x = UInt<3>("h7") ;CHECK: Finished Constant Propagation circuit top : diff --git a/test/passes/const-prop/rsh.fir b/test/passes/const-prop/rsh.fir index 4159899f..5ed8b1be 100644 --- a/test/passes/const-prop/rsh.fir +++ b/test/passes/const-prop/rsh.fir @@ -1,8 +1,8 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Constant Propagation -;CHECK: x <= UInt("h1f") -;CHECK: y <= SInt("h20") +;CHECK: x <= UInt<5>("h1f") +;CHECK: y <= SInt<6>("h20") ;CHECK: Finished Constant Propagation circuit top : |