From e985d47312458459e9ebe42fe99b5a063c08e637 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sun, 31 Jan 2016 12:59:31 -0800
Subject: Changed stanza output of UInt/SInt to include widths. Made tests
 match accordingly

---
 test/passes/const-prop/bits.fir | 2 +-
 test/passes/const-prop/rsh.fir  | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'test/passes/const-prop')

diff --git a/test/passes/const-prop/bits.fir b/test/passes/const-prop/bits.fir
index 78c450a9..74aa19de 100644
--- a/test/passes/const-prop/bits.fir
+++ b/test/passes/const-prop/bits.fir
@@ -1,7 +1,7 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Constant Propagation
-;CHECK: node x = UInt("h7")
+;CHECK: node x = UInt<3>("h7")
 ;CHECK: Finished Constant Propagation
 
 circuit top :
diff --git a/test/passes/const-prop/rsh.fir b/test/passes/const-prop/rsh.fir
index 4159899f..5ed8b1be 100644
--- a/test/passes/const-prop/rsh.fir
+++ b/test/passes/const-prop/rsh.fir
@@ -1,8 +1,8 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 
 ;CHECK: Constant Propagation
-;CHECK: x <= UInt("h1f")
-;CHECK: y <= SInt("h20")
+;CHECK: x <= UInt<5>("h1f")
+;CHECK: y <= SInt<6>("h20")
 ;CHECK: Finished Constant Propagation
 
 circuit top :
-- 
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