diff options
| author | azidar | 2015-12-10 12:27:56 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 0246ab2479724fb0118bb7a25577c71e2a038223 (patch) | |
| tree | e3a5aa22a3712d28b5b094580cd50babd6520e2f /test/features/Stop.fir | |
| parent | be78d49aa01c097978f69a3b022acb2047fdf438 (diff) | |
WIP, hit semantic bug in WSubAccess
Diffstat (limited to 'test/features/Stop.fir')
| -rw-r--r-- | test/features/Stop.fir | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/test/features/Stop.fir b/test/features/Stop.fir index 16e25416..d0957324 100644 --- a/test/features/Stop.fir +++ b/test/features/Stop.fir @@ -1,6 +1,6 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -;CHECK: Lower To Ground +;CHECK: Expand Whens circuit Top : module Top : @@ -8,14 +8,13 @@ circuit Top : input q : UInt<1> input clk : Clock when p : - stop(clk,0) + stop(clk,UInt(1),0) when q : - stop(clk,1) - stop(clk,3) - -;CHECK: when p : stop(clk, 0) -;CHECK: when q : stop(clk, 1) -;CHECK: stop(clk, 3) + stop(clk,UInt(1),1) + stop(clk,UInt(1),3) +;CHECK: stop(clk, and(p, UInt("h1")), 0) +;CHECK: stop(clk, and(q, UInt("h1")), 1) +;CHECK: stop(clk, UInt("h1"), 3) ;CHECK: Done! |