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authorazidar2016-01-28 12:12:02 -0800
committerazidar2016-01-28 12:12:02 -0800
commit9ed79a822f7f406c55af8082da04cb7739e772eb (patch)
tree02b10696dd0a03faf54c8eafa046855ccfc26e8f /test/errors
parentb7dcc8ccbb1459a604353a8137081a9b156d276e (diff)
parent094c6b8e7b40a3c613547d6127b449d0b1503db3 (diff)
Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl
Diffstat (limited to 'test/errors')
-rw-r--r--test/errors/gender/BulkWrong.fir2
-rw-r--r--test/errors/high-form/RemoveChar.fir2
2 files changed, 2 insertions, 2 deletions
diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir
index 1becd104..c9b24aa2 100644
--- a/test/errors/gender/BulkWrong.fir
+++ b/test/errors/gender/BulkWrong.fir
@@ -18,7 +18,7 @@ circuit BTB :
in.y <- w.y
in.y.z <- w.y.z
- w.x <= addw(in.x,in.y.z)
+ w.x <= add(in.x,in.y.z)
out <- in
in.y <- out.y
diff --git a/test/errors/high-form/RemoveChar.fir b/test/errors/high-form/RemoveChar.fir
index 9341468c..aa5e8227 100644
--- a/test/errors/high-form/RemoveChar.fir
+++ b/test/errors/high-form/RemoveChar.fir
@@ -6,7 +6,7 @@ circuit Top :
wire x_1 : UInt<1>
x_1 <= UInt(1)
wire x : UInt<1>
- x <= addw(addw(UInt(1),UInt(1)),UInt(1))
+ x <= add(add(UInt(1),UInt(1)),UInt(1))