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| author | azidar | 2015-05-18 20:33:23 -0700 |
|---|---|---|
| committer | azidar | 2015-05-18 20:33:23 -0700 |
| commit | 14bb9cda8352388bcd33ba9ca2700805dc51639f (patch) | |
| tree | a9bf8f46948aedadae0fe8e6c423ec48b643786e /test/errors/parser | |
| parent | 3336e6beb23e1ba883097eac0c0000269bf8ebfa (diff) | |
First pass at a Verilog Backend. Not tested, but compiles and generates reasonable verilog. Requires inlining, future versions will instantiate modules
Diffstat (limited to 'test/errors/parser')
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