diff options
| author | azidar | 2015-08-25 15:37:53 -0700 |
|---|---|---|
| committer | azidar | 2015-08-25 15:37:53 -0700 |
| commit | 40bf74bfdf4d07f0d7171b77ae34004eb9c1fa11 (patch) | |
| tree | bc64373fa3c59972731fa9167d8f65b47ccae9d5 /test/errors/init | |
| parent | 9fd6d47c5ee82e4dac924e15b60f2a519d566b14 (diff) | |
Fixed bug in split expression that leaked connect statements out of a conditional assignment
Diffstat (limited to 'test/errors/init')
| -rw-r--r-- | test/errors/init/Output.fir | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/test/errors/init/Output.fir b/test/errors/init/Output.fir new file mode 100644 index 00000000..f28d1e0b --- /dev/null +++ b/test/errors/init/Output.fir @@ -0,0 +1,10 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; CHECK: Reference y is not fully initialized. + +circuit Top : + module Top : + input clk : Clock + wire y : UInt<1> + + when UInt(0) : + y := UInt(1) |