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| author | azidar | 2015-08-25 14:13:00 -0700 |
|---|---|---|
| committer | azidar | 2015-08-25 14:13:13 -0700 |
| commit | eb1ab67b6cc3fd4a549da563bf643bd519d7562e (patch) | |
| tree | a21f0ca828398a33a68f38209429cc6beed86edc /test/errors/high-form | |
| parent | 6cd96b6315c32bbf6c4ace28197ff1d4be86a129 (diff) | |
Added width check pass with tests. #22.
Diffstat (limited to 'test/errors/high-form')
| -rw-r--r-- | test/errors/high-form/NegWidth.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/errors/high-form/NegWidth.fir b/test/errors/high-form/NegWidth.fir index 9b055228..1eb54a34 100644 --- a/test/errors/high-form/NegWidth.fir +++ b/test/errors/high-form/NegWidth.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Width cannot be negative. +; CHECK: Width cannot be negative or zero. circuit Top : module Top : |