Added <>. Added additional checks for primops. Added new chisel3 files.

3 files changed, 25 insertions, 0 deletions

diff --git a/test/errors/high-form/NegVecSize.fir b/test/errors/high-form/NegVecSize.fir
new file mode 100644
index 00000000..16fae565
--- /dev/null
+++ b/test/errors/high-form/NegVecSize.fir
@@ -0,0 +1,7 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Vector type size cannot be negative
+
+circuit Top : 
+  module Top : 
+    wire x : UInt<3>[-5]
+
diff --git a/test/errors/high-form/NegWidth.fir b/test/errors/high-form/NegWidth.fir
new file mode 100644
index 00000000..3f305301
--- /dev/null
+++ b/test/errors/high-form/NegWidth.fir
@@ -0,0 +1,7 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Width cannot be negative.
+
+circuit Top : 
+  module Top : 
+    wire x : UInt<-3>
+
diff --git a/test/errors/high-form/NumArgs.fir b/test/errors/high-form/NumArgs.fir
new file mode 100644
index 00000000..4dc8ad46
--- /dev/null
+++ b/test/errors/high-form/NumArgs.fir
@@ -0,0 +1,11 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Primop mux requires 3 expression arguments.
+; CHECK: Primop add requires 2 expression arguments.
+; CHECK: Primop bits requires 2 integer arguments.
+
+circuit Top : 
+  module Top : 
+    node x = mux(UInt(1),UInt(1))
+    node y = add(SInt(1),UInt(1),UInt(1))
+    node z = bits(UInt(1),1,2,3)
+