diff options
| author | azidar | 2015-07-13 16:22:43 -0700 |
|---|---|---|
| committer | azidar | 2015-07-13 16:22:43 -0700 |
| commit | 9b6d8514a3be860562d8d524fa425c87d1537e8a (patch) | |
| tree | ca46b9703046e23068860b5c5d8d6af01296c000 /test/errors/high-form/RemoveScope.fir | |
| parent | 1ed6d4a47c92072b12db4b784f239071e4928049 (diff) | |
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/errors/high-form/RemoveScope.fir')
| -rw-r--r-- | test/errors/high-form/RemoveScope.fir | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir new file mode 100644 index 00000000..1d9f7ef6 --- /dev/null +++ b/test/errors/high-form/RemoveScope.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; CHECK: Done! + +circuit Top : + module Top : + wire x : UInt<1> + node p = UInt(1) + when p : + wire x : UInt<1> + x := UInt(1) + node y = add(x,UInt(1)) + else : + wire x : UInt<1> + x := UInt(1) + node z = add(x,UInt(1)) + x := UInt(1) + node w = add(x,UInt(1)) |