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| author | azidar | 2016-01-24 16:30:50 -0800 |
|---|---|---|
| committer | azidar | 2016-01-24 16:30:50 -0800 |
| commit | 8265e2e67e39f2d313a74bccb6dd45d85f706f3a (patch) | |
| tree | 744a5eea0e86a43aaeb720fc545bcfe80840b139 /test/errors/high-form/NumArgs.fir | |
| parent | 63b3668414bfea1c3bdd651a552d5fa7b5d6b9c4 (diff) | |
Added muxing on passive aggregate types
Diffstat (limited to 'test/errors/high-form/NumArgs.fir')
| -rw-r--r-- | test/errors/high-form/NumArgs.fir | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/test/errors/high-form/NumArgs.fir b/test/errors/high-form/NumArgs.fir index 6c083905..7db78509 100644 --- a/test/errors/high-form/NumArgs.fir +++ b/test/errors/high-form/NumArgs.fir @@ -1,11 +1,9 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Primop mux requires 3 expression arguments. ; CHECK: Primop add requires 2 expression arguments. ; CHECK: Primop bits requires 2 integer arguments. circuit Top : module Top : - node x = mux(UInt(1),UInt(1)) node y = add(SInt(1),UInt(1),UInt(1)) node z = bits(UInt(1),1,2,3) |