diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/errors/gender/ReadOutput.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/errors/gender/ReadOutput.fir')
| -rw-r--r-- | test/errors/gender/ReadOutput.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/errors/gender/ReadOutput.fir b/test/errors/gender/ReadOutput.fir index 14ac75c1..fd3607d0 100644 --- a/test/errors/gender/ReadOutput.fir +++ b/test/errors/gender/ReadOutput.fir @@ -6,7 +6,7 @@ circuit BTB : output out : {x : UInt<1>, flip y : UInt<1>} wire w : {x : UInt<1>, flip y : UInt<1>} - w.x := UInt(1) - w.y := UInt(1) - out.x := UInt(1) - w <> out + w.x <= UInt(1) + w.y <= UInt(1) + out.x <= UInt(1) + w <- out |