merge + fix trim to use correct bits operands

1 files changed, 31 insertions, 0 deletions

diff --git a/test/chisel3/VendingMachine.fir b/test/chisel3/VendingMachine.fir
new file mode 100644
index 00000000..a1149dbc
--- /dev/null
+++ b/test/chisel3/VendingMachine.fir
@@ -0,0 +1,31 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit VendingMachine : 
+  module VendingMachine : 
+    output valid : UInt<1>
+    input nickel : UInt<1>
+    input dime : UInt<1>
+    
+    reg state : UInt<3>
+    on-reset state := UInt<3>(0)
+    node T_22 = eq(state, UInt<3>(0))
+    when T_22 : 
+      when nickel : state := UInt<3>(1)
+      when dime : state := UInt<3>(2)
+    node T_23 = eq(state, UInt<3>(1))
+    when T_23 : 
+      when nickel : state := UInt<3>(2)
+      when dime : state := UInt<3>(3)
+    node T_24 = eq(state, UInt<3>(2))
+    when T_24 : 
+      when nickel : state := UInt<3>(3)
+      when dime : state := UInt<3>(4)
+    node T_25 = eq(state, UInt<3>(3))
+    when T_25 : 
+      when nickel : state := UInt<3>(4)
+      when dime : state := UInt<3>(4)
+    node T_26 = eq(state, UInt<3>(4))
+    when T_26 : state := UInt<3>(0)
+    node T_27 = eq(state, UInt<3>(4))
+    valid := T_27