diff options
| author | azidar | 2015-06-03 20:39:41 -0700 |
|---|---|---|
| committer | azidar | 2015-06-03 20:39:41 -0700 |
| commit | 887d785ecc2ba7c363194cef89b72bc026c81cf9 (patch) | |
| tree | 350224acd106b5e5a4bbfccef793ac412a86b556 /test/chisel3/Tile.fir | |
| parent | 0a0c2d7c13c5beaa7c5132963112cc9e747ff287 (diff) | |
Fixed verilog backend bugs. Passes ALU. Fails Datapath
Diffstat (limited to 'test/chisel3/Tile.fir')
| -rw-r--r-- | test/chisel3/Tile.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/chisel3/Tile.fir b/test/chisel3/Tile.fir index 01d78cd0..e85bd56b 100644 --- a/test/chisel3/Tile.fir +++ b/test/chisel3/Tile.fir @@ -195,12 +195,12 @@ circuit Tile : when T_1676 : node T_1677 = eq(addr, UInt<12>(1310)) when T_1677 : - node T_1678 = dshl(UInt<1>(1), src) + node T_1678 = dshl(UInt<1>(1), bits(src,5,0)) node T_1679 = bit-or(data, T_1678) reg_tohost := T_1679 node T_1680 = eq(addr, UInt<12>(1290)) when T_1680 : - node T_1681 = dshl(UInt<1>(1), src) + node T_1681 = dshl(UInt<1>(1), bits(src,5,0)) node T_1682 = bit-or(data, T_1681) reg_status := T_1682 node T_1683 = eq(cmd, UInt<2>(3)) @@ -209,12 +209,12 @@ circuit Tile : when T_1685 : node T_1686 = eq(addr, UInt<12>(1310)) when T_1686 : - node T_1687 = dshl(UInt<1>(0), src) + node T_1687 = dshl(UInt<1>(0), bits(src,5,0)) node T_1688 = bit-and(data, T_1687) reg_tohost := T_1688 node T_1689 = eq(addr, UInt<12>(1290)) when T_1689 : - node T_1690 = dshl(UInt<1>(0), src) + node T_1690 = dshl(UInt<1>(0), bits(src,5,0)) node T_1691 = bit-and(data, T_1690) reg_status := T_1691 module Datapath : |