Fixed verilog backend bugs. Passes ALU. Fails Datapath

4 files changed, 26 insertions, 26 deletions

diff --git a/test/chisel3/ALUTop.fir b/test/chisel3/ALUTop.fir
index 5ebcbccc..2cb4c32e 100644
--- a/test/chisel3/ALUTop.fir
+++ b/test/chisel3/ALUTop.fir
@@ -12,7 +12,7 @@ circuit ALUTop :
     node shamt = bits(B, 4, 0)
     node T_157 = add-wrap(A, B)
     node T_158 = sub-wrap(A, B)
-    node T_159 = convert(A)
+    node T_159 = as-SInt(A)
     node T_160 = dshr(T_159, shamt)
     node T_161 = as-UInt(T_160)
     node T_162 = dshr(A, shamt)
@@ -100,19 +100,19 @@ circuit ALUTop :
     node alu_op2 = mux(T_233, UInt<4>(11), T_232)
     alu_op := alu_op2
   module ALUTop : 
-    input B : UInt<32>
-    output out : UInt<32>
-    input A : UInt<32>
-    input opcode : UInt<7>
-    input funct : UInt<3>
-    input add_rshift_type : UInt<1>
+    input io_B : UInt<32>
+    output io_out : UInt<32>
+    input io_A : UInt<32>
+    input io_opcode : UInt<7>
+    input io_funct : UInt<3>
+    input io_add_rshift_type : UInt<1>
     
     inst alu of ALU
     inst alu_dec of ALUdec
-    alu_dec.opcode := opcode
-    alu_dec.funct := funct
-    alu_dec.add_rshift_type := add_rshift_type
-    alu.A := A
-    alu.B := B
-    out := alu.out
+    alu_dec.opcode := io_opcode
+    alu_dec.funct := io_funct
+    alu_dec.add_rshift_type := io_add_rshift_type
+    alu.A := io_A
+    alu.B := io_B
+    io_out := alu.out
     alu.alu_op := alu_dec.alu_op
diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir
index 06010573..b2062c1d 100644
--- a/test/chisel3/Core.fir
+++ b/test/chisel3/Core.fir
@@ -12,7 +12,7 @@ circuit Core :
     node shamt = bits(B, 4, 0)
     node T_1224 = add-wrap(A, B)
     node T_1225 = sub-wrap(A, B)
-    node T_1226 = convert(A)
+    node T_1226 = as-SInt(A)
     node T_1227 = dshr(T_1226, shamt)
     node T_1228 = as-UInt(T_1227)
     node T_1229 = dshr(A, shamt)
@@ -195,12 +195,12 @@ circuit Core :
     when T_1346 : 
       node T_1347 = eq(addr, UInt<12>(1310))
       when T_1347 : 
-        node T_1348 = dshl(UInt<1>(1), src)
+        node T_1348 = dshl(UInt<1>(1), bits(src,5,0))
         node T_1349 = bit-or(data, T_1348)
         reg_tohost := T_1349
       node T_1350 = eq(addr, UInt<12>(1290))
       when T_1350 : 
-        node T_1351 = dshl(UInt<1>(1), src)
+        node T_1351 = dshl(UInt<1>(1), bits(src,5,0))
         node T_1352 = bit-or(data, T_1351)
         reg_status := T_1352
     node T_1353 = eq(cmd, UInt<2>(3))
@@ -209,12 +209,12 @@ circuit Core :
     when T_1355 : 
       node T_1356 = eq(addr, UInt<12>(1310))
       when T_1356 : 
-        node T_1357 = dshl(UInt<1>(0), src)
+        node T_1357 = dshl(UInt<1>(0), bits(src,5,0))
         node T_1358 = bit-and(data, T_1357)
         reg_tohost := T_1358
       node T_1359 = eq(addr, UInt<12>(1290))
       when T_1359 : 
-        node T_1360 = dshl(UInt<1>(0), src)
+        node T_1360 = dshl(UInt<1>(0), bits(src,5,0))
         node T_1361 = bit-and(data, T_1360)
         reg_status := T_1361
   module Datapath : 
diff --git a/test/chisel3/Datapath.fir b/test/chisel3/Datapath.fir
index 10643549..c02eeae6 100644
--- a/test/chisel3/Datapath.fir
+++ b/test/chisel3/Datapath.fir
@@ -195,12 +195,12 @@ circuit Datapath :
     when T_555 : 
       node T_556 = eq(addr, UInt<12>(1310))
       when T_556 : 
-        node T_557 = dshl(UInt<1>(1), src)
+        node T_557 = dshl(UInt<1>(1), bits(src,5,0))
         node T_558 = bit-or(data, T_557)
         reg_tohost := T_558
       node T_559 = eq(addr, UInt<12>(1290))
       when T_559 : 
-        node T_560 = dshl(UInt<1>(1), src)
+        node T_560 = dshl(UInt<1>(1), bits(src,5,0))
         node T_561 = bit-or(data, T_560)
         reg_status := T_561
     node T_562 = eq(cmd, UInt<2>(3))
@@ -209,12 +209,12 @@ circuit Datapath :
     when T_564 : 
       node T_565 = eq(addr, UInt<12>(1310))
       when T_565 : 
-        node T_566 = dshl(UInt<1>(0), src)
+        node T_566 = dshl(UInt<1>(0), bits(src,5,0))
         node T_567 = bit-and(data, T_566)
         reg_tohost := T_567
       node T_568 = eq(addr, UInt<12>(1290))
       when T_568 : 
-        node T_569 = dshl(UInt<1>(0), src)
+        node T_569 = dshl(UInt<1>(0), bits(src,5,0))
         node T_570 = bit-and(data, T_569)
         reg_status := T_570
   module Datapath : 
diff --git a/test/chisel3/Tile.fir b/test/chisel3/Tile.fir
index 01d78cd0..e85bd56b 100644
--- a/test/chisel3/Tile.fir
+++ b/test/chisel3/Tile.fir
@@ -195,12 +195,12 @@ circuit Tile :
     when T_1676 : 
       node T_1677 = eq(addr, UInt<12>(1310))
       when T_1677 : 
-        node T_1678 = dshl(UInt<1>(1), src)
+        node T_1678 = dshl(UInt<1>(1), bits(src,5,0))
         node T_1679 = bit-or(data, T_1678)
         reg_tohost := T_1679
       node T_1680 = eq(addr, UInt<12>(1290))
       when T_1680 : 
-        node T_1681 = dshl(UInt<1>(1), src)
+        node T_1681 = dshl(UInt<1>(1), bits(src,5,0))
         node T_1682 = bit-or(data, T_1681)
         reg_status := T_1682
     node T_1683 = eq(cmd, UInt<2>(3))
@@ -209,12 +209,12 @@ circuit Tile :
     when T_1685 : 
       node T_1686 = eq(addr, UInt<12>(1310))
       when T_1686 : 
-        node T_1687 = dshl(UInt<1>(0), src)
+        node T_1687 = dshl(UInt<1>(0), bits(src,5,0))
         node T_1688 = bit-and(data, T_1687)
         reg_tohost := T_1688
       node T_1689 = eq(addr, UInt<12>(1290))
       when T_1689 : 
-        node T_1690 = dshl(UInt<1>(0), src)
+        node T_1690 = dshl(UInt<1>(0), bits(src,5,0))
         node T_1691 = bit-and(data, T_1690)
         reg_status := T_1691
   module Datapath :