diff options
| author | azidar | 2015-06-04 14:56:18 -0700 |
|---|---|---|
| committer | azidar | 2015-06-04 14:56:18 -0700 |
| commit | 06f57fefe8258c7d8149156db7ca01a66f207a5d (patch) | |
| tree | 2598d83574f3675e42e763c18fbb6793b779c8df /test/chisel3/Tile.fir | |
| parent | d86272ca9238c12e80e78938bc1dd5a1dc8532da (diff) | |
Fixed fir files so they correctly compile to verilog! Front-end needs to generate as-SInt instead of convert, always. Added fast build to Makefile
Diffstat (limited to 'test/chisel3/Tile.fir')
| -rw-r--r-- | test/chisel3/Tile.fir | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/test/chisel3/Tile.fir b/test/chisel3/Tile.fir index e85bd56b..b84684db 100644 --- a/test/chisel3/Tile.fir +++ b/test/chisel3/Tile.fir @@ -12,14 +12,14 @@ circuit Tile : node shamt = bits(B, 4, 0) node T_1554 = add-wrap(A, B) node T_1555 = sub-wrap(A, B) - node T_1556 = convert(A) + node T_1556 = as-SInt(A) node T_1557 = dshr(T_1556, shamt) node T_1558 = as-UInt(T_1557) node T_1559 = dshr(A, shamt) node T_1560 = dshl(A, shamt) node T_1561 = bits(T_1560, 31, 0) - node T_1562 = convert(A) - node T_1563 = convert(B) + node T_1562 = as-SInt(A) + node T_1563 = as-SInt(B) node T_1564 = lt(T_1562, T_1563) node T_1565 = as-UInt(T_1564) node T_1566 = lt(A, B) @@ -64,8 +64,8 @@ circuit Tile : node eq = eq(rs1, rs2) node neq = bit-not(eq) - node T_1597 = convert(rs1) - node T_1598 = convert(rs2) + node T_1597 = as-SInt(rs1) + node T_1598 = as-SInt(rs2) node lt = lt(T_1597, T_1598) node ge = bit-not(lt) node ltu = lt(rs1, rs2) @@ -120,11 +120,11 @@ circuit Tile : input sel : UInt<3> node T_1628 = bits(inst, 31, 20) - node Iimm = convert(T_1628) + node Iimm = as-SInt(T_1628) node T_1629 = bits(inst, 31, 25) node T_1630 = bits(inst, 11, 7) node T_1631 = cat(T_1629, T_1630) - node Simm = convert(T_1631) + node Simm = as-SInt(T_1631) node T_1632 = bit(inst, 31) node T_1633 = bit(inst, 7) node T_1634 = bits(inst, 30, 25) @@ -133,10 +133,10 @@ circuit Tile : node T_1637 = cat(T_1635, UInt<1>(0)) node T_1638 = cat(T_1634, T_1637) node T_1639 = cat(T_1636, T_1638) - node Bimm = convert(T_1639) + node Bimm = as-SInt(T_1639) node T_1640 = bits(inst, 31, 12) node T_1641 = cat(T_1640, UInt<12>(0)) - node Uimm = convert(T_1641) + node Uimm = as-SInt(T_1641) node T_1642 = bit(inst, 31) node T_1643 = bits(inst, 19, 12) node T_1644 = bit(inst, 20) @@ -147,10 +147,10 @@ circuit Tile : node T_1649 = cat(T_1646, UInt<1>(0)) node T_1650 = cat(T_1645, T_1649) node T_1651 = cat(T_1648, T_1650) - node Jimm = convert(T_1651) + node Jimm = as-SInt(T_1651) node T_1652 = bits(inst, 19, 15) node T_1653 = pad(T_1652, 32) - node Zimm = convert(T_1653) + node Zimm = as-SInt(T_1653) node T_1654 = eq(UInt<3>(3), sel) node T_1655 = mux(T_1654, Jimm, Zimm) node T_1656 = eq(UInt<3>(2), sel) @@ -330,11 +330,11 @@ circuit Tile : node loffset = bit-or(T_1739, T_1741) node lshift = dshr(dcache.dout, loffset) node T_1742 = bits(lshift, 15, 0) - node T_1743 = convert(T_1742) + node T_1743 = as-SInt(T_1742) node T_1744 = pad(T_1743, 32) node T_1745 = as-UInt(T_1744) node T_1746 = bits(lshift, 7, 0) - node T_1747 = convert(T_1746) + node T_1747 = as-SInt(T_1746) node T_1748 = pad(T_1747, 32) node T_1749 = as-UInt(T_1748) node T_1750 = bits(lshift, 15, 0) |