Removed old chisel3 tests that all failed for syntax reasons. Tests should now be small examples, categorized by either passes, errors, or features.

1 files changed, 0 insertions, 18 deletions

diff --git a/test/chisel3/Test.fir b/test/chisel3/Test.fir
deleted file mode 100644
index f0d8f80e..00000000
--- a/test/chisel3/Test.fir
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
-
-circuit Test : 
-  module Test : 
-     input clk : Clock
-     input reset : UInt<1>
-     input falling : UInt<1>
-
-     reg hold : UInt<100>, clk, UInt(1)
-
-     hold := UInt("h42")
-     when reset :
-        hold := UInt("h7f")
-     else :
-        when falling :
-           hold := UInt("h8f")
-