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authorazidar2015-07-07 10:13:29 -0700
committerazidar2015-07-14 11:29:55 -0700
commitd696dd01de8a1a83a376c719490f475be991f387 (patch)
treeca5d8f21c0f7787cc6eb00e078f0c0ae1e20a182 /test/chisel3/Tbl.fir
parent3c8f283b445ca99d4ed4c1e04e2bc8bdcdbd72f6 (diff)
Pass most tests. The ones that do not pass are not expected to, yet
Diffstat (limited to 'test/chisel3/Tbl.fir')
-rw-r--r--test/chisel3/Tbl.fir4
1 files changed, 2 insertions, 2 deletions
diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir
index e7397f61..013fd098 100644
--- a/test/chisel3/Tbl.fir
+++ b/test/chisel3/Tbl.fir
@@ -11,9 +11,9 @@ circuit Tbl :
cmem m : UInt<10>[256]
o := UInt<1>(0)
when we :
- accessor T_13 = m[i]
+ infer accessor T_13 = m[i]
node T_14 = bits(d, 9, 0)
T_13 := T_14
else :
- accessor T_15 = m[i]
+ infer accessor T_15 = m[i]
o := T_15