diff options
| author | azidar | 2015-07-07 10:13:29 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | d696dd01de8a1a83a376c719490f475be991f387 (patch) | |
| tree | ca5d8f21c0f7787cc6eb00e078f0c0ae1e20a182 /test/chisel3/Risc.fir | |
| parent | 3c8f283b445ca99d4ed4c1e04e2bc8bdcdbd72f6 (diff) | |
Pass most tests. The ones that do not pass are not expected to, yet
Diffstat (limited to 'test/chisel3/Risc.fir')
| -rw-r--r-- | test/chisel3/Risc.fir | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/chisel3/Risc.fir b/test/chisel3/Risc.fir index 425f8a91..a1ba01b9 100644 --- a/test/chisel3/Risc.fir +++ b/test/chisel3/Risc.fir @@ -14,23 +14,23 @@ circuit Risc : cmem code : UInt<32>[256] reg pc : UInt<8> on-reset pc := UInt<8>(0) - accessor inst = code[pc] + infer accessor inst = code[pc] node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) node rai = bits(inst, 15, 8) node rbi = bits(inst, 7, 0) node T_51 = eq(rai, UInt<1>(0)) - accessor T_52 = file[rai] + infer accessor T_52 = file[rai] node ra = mux(T_51, UInt<1>(0), T_52) node T_53 = eq(rbi, UInt<1>(0)) - accessor T_54 = file[rbi] + infer accessor T_54 = file[rbi] node rb = mux(T_53, UInt<1>(0), T_54) wire rc : UInt<32> valid := UInt<1>(0) out := UInt<1>(0) rc := UInt<1>(0) when isWr : - accessor T_55 = code[wrAddr] + infer accessor T_55 = code[wrAddr] T_55 := wrData else : when boot : pc := UInt<1>(0) else : @@ -47,7 +47,7 @@ circuit Risc : node T_61 = eq(rci, UInt<8>(255)) when T_61 : valid := UInt<1>(1) else : - accessor T_62 = file[rci] + infer accessor T_62 = file[rci] T_62 := rc node T_63 = add-wrap(pc, UInt<1>(1)) pc := T_63 |