Removed old chisel3 tests that all failed for syntax reasons. Tests should now be small examples, categorized by either passes, errors, or features.

1 files changed, 0 insertions, 29 deletions

diff --git a/test/chisel3/RegisterVecShift.fir b/test/chisel3/RegisterVecShift.fir
deleted file mode 100644
index 3d51ece3..00000000
--- a/test/chisel3/RegisterVecShift.fir
+++ /dev/null
@@ -1,29 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
-
-circuit RegisterVecShift : 
-  module RegisterVecShift : 
-    input load : UInt<1>
-    output out : UInt<4>
-    input shift : UInt<1>
-    input ins : UInt<4>[4]
-    
-    reg delays : UInt<4>[4]
-    when reset : 
-      wire T_33 : UInt<4>[4]
-      T_33[0] := UInt<4>(0)
-      T_33[1] := UInt<4>(0)
-      T_33[2] := UInt<4>(0)
-      T_33[3] := UInt<4>(0)
-      delays := T_33
-    when load : 
-      delays[0] := ins[0]
-      delays[1] := ins[1]
-      delays[2] := ins[2]
-      delays[3] := ins[3]
-    else : when shift : 
-        delays[0] := ins[0]
-        delays[1] := delays[0]
-        delays[2] := delays[1]
-        delays[3] := delays[2]
-    out := delays[3]