Removed old chisel3 tests that all failed for syntax reasons. Tests should now be small examples, categorized by either passes, errors, or features.

1 files changed, 0 insertions, 19 deletions

diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir
deleted file mode 100644
index 886a01ba..00000000
--- a/test/chisel3/Outer.fir
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
-
-circuit Outer : 
-  module Inner : 
-    input in : UInt<8>
-    output out : UInt<8>
-    
-    node T_15 = add-wrap(in, UInt<1>(1))
-    out := T_15
-  module Outer : 
-    input in : UInt<8>
-    output out : UInt<8>
-    
-    inst T_16 of Inner
-    T_16.in := in
-    node T_17 = mul(T_16.out, UInt<2>(2))
-    node T_18 = bits(T_17, 7, 0)
-    out := T_18