diff options
| author | jackbackrack | 2015-06-02 08:47:40 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-06-02 08:47:40 -0700 |
| commit | b178ca42fd9d4f7b94d80c01cd810bf18da9ebc8 (patch) | |
| tree | 033e197aa2e297187e21712faf1957eb405b435b /test/chisel3/ModuleWire.fir | |
| parent | e668a13b285c87678a708a8af5bee2cfa0f7645b (diff) | |
| parent | 8fc826a2770f46d63d8d7b1bccf14d2bf6e6b7cd (diff) | |
merge + fix trim to use correct bits operands
Diffstat (limited to 'test/chisel3/ModuleWire.fir')
| -rw-r--r-- | test/chisel3/ModuleWire.fir | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/chisel3/ModuleWire.fir b/test/chisel3/ModuleWire.fir new file mode 100644 index 00000000..fefe42bd --- /dev/null +++ b/test/chisel3/ModuleWire.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done! + +circuit ModuleWire : + module Inc : + input in : UInt<32> + output out : UInt<32> + + node T_12 = add-wrap(in, UInt<1>(1)) + out := T_12 + module ModuleWire : + input in : UInt<32> + output out : UInt<32> + + inst T_13 of Inc + T_13.in := in + out := T_13.out |