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authorazidar2015-04-24 14:46:44 -0700
committerazidar2015-04-24 14:46:44 -0700
commitbd8b9669d1cdc4898be9d38ca9c492866d927d77 (patch)
treefbaac47d11092bbd61af38b6692e5dffc352028c /test/chisel3/ModuleVec.fir
parent1652c3cf8329246fa372513fb0d2bdf53ddd227f (diff)
Fixed width inference bug where later constraints on the output width were not propogating to the input widths, for primops
Diffstat (limited to 'test/chisel3/ModuleVec.fir')
0 files changed, 0 insertions, 0 deletions