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authorjackbackrack2015-04-20 15:21:30 -0700
committerjackbackrack2015-04-20 15:21:30 -0700
commit6204b6d44aef2f47a8009ad06dfd4e09ce7ce950 (patch)
tree8795de870f20086b0615f7c402c234b79e6a71a0 /test/chisel3/Counter.fir
parent5298af3dffcd0985922a2a8317fa6a67e192a9c0 (diff)
parent7617e33993abf9f6be357e0261755a4736c2e085 (diff)
merge
Diffstat (limited to 'test/chisel3/Counter.fir')
-rw-r--r--test/chisel3/Counter.fir20
1 files changed, 0 insertions, 20 deletions
diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir
deleted file mode 100644
index 55091d7f..00000000
--- a/test/chisel3/Counter.fir
+++ /dev/null
@@ -1,20 +0,0 @@
-;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
-;CHECK: To Flo
-circuit Counter :
- module Counter :
- input inc : UInt(1)
- output tot : UInt(8)
- input amt : UInt(4)
-
- node T_13 = UInt(255, 8)
- node T_14 = UInt(0, 8)
- reg T_15 : UInt(8)
- T_15.init := T_14
- when inc :
- node T_16 = add-wrap(T_15, amt)
- node T_17 = gt(T_16, T_13)
- node T_18 = UInt(0, 1)
- node T_19 = mux(T_17, T_18, T_16)
- T_15 := T_19
- tot := T_15
-;CHECK: Finished To Flo