diff options
| author | jackbackrack | 2015-04-13 18:24:37 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-04-13 18:24:37 -0700 |
| commit | e6beb7b3bbb745a7c7fde616bb349df1bdb7b764 (patch) | |
| tree | 392bc8ed6dc497aaa98329133bd135d729426e3d /test/chisel3/ComplexAssign.fir | |
| parent | c140b1ffbcf7fb5b2bb05e93388b2c79f2ddf9f9 (diff) | |
new chisel3 tests
Diffstat (limited to 'test/chisel3/ComplexAssign.fir')
| -rw-r--r-- | test/chisel3/ComplexAssign.fir | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir new file mode 100644 index 00000000..2cf52370 --- /dev/null +++ b/test/chisel3/ComplexAssign.fir @@ -0,0 +1,15 @@ +circuit ComplexAssign : + module ComplexAssign : + input in : {output re : UInt(10), output im : UInt(10)} + output out : {output re : UInt(10), output im : UInt(10)} + input e : UInt(1) + when e : + wire T_19 : {output re : UInt(10), output im : UInt(10)} + T_19 := in + out.re := T_19.re + out.im := T_19.im + else : + node T_20 : UInt(1) = UInt(0, 1) + out.re := T_20 + node T_21 : UInt(1) = UInt(0, 1) + out.im := T_21
\ No newline at end of file |