From e6beb7b3bbb745a7c7fde616bb349df1bdb7b764 Mon Sep 17 00:00:00 2001
From: jackbackrack
Date: Mon, 13 Apr 2015 18:24:37 -0700
Subject: new chisel3 tests

---
 test/chisel3/ComplexAssign.fir | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 test/chisel3/ComplexAssign.fir

(limited to 'test/chisel3/ComplexAssign.fir')

diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir
new file mode 100644
index 00000000..2cf52370
--- /dev/null
+++ b/test/chisel3/ComplexAssign.fir
@@ -0,0 +1,15 @@
+circuit ComplexAssign : 
+  module ComplexAssign : 
+    input in : {output re : UInt(10), output im : UInt(10)}
+    output out : {output re : UInt(10), output im : UInt(10)}
+    input e : UInt(1)
+    when e : 
+      wire T_19 : {output re : UInt(10), output im : UInt(10)}
+      T_19 := in
+      out.re := T_19.re
+      out.im := T_19.im
+     else : 
+      node T_20 : UInt(1) = UInt(0, 1)
+      out.re := T_20
+      node T_21 : UInt(1) = UInt(0, 1)
+      out.im := T_21
\ No newline at end of file
-- 
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