Added <>. Added additional checks for primops. Added new chisel3 files.

1 files changed, 16 insertions, 0 deletions

diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir
new file mode 100644
index 00000000..c1dc41cd
--- /dev/null
+++ b/test/chisel3/ComplexAssign.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit ComplexAssign : 
+  module ComplexAssign : 
+    input in : {re : UInt<10>, im : UInt<10>}
+    output out : {re : UInt<10>, im : UInt<10>}
+    input e : UInt<1>
+    when e : 
+      wire T_18 : {re : UInt<10>, im : UInt<10>}
+      T_18 := in
+      out.re := T_18.re
+      out.im := T_18.im
+    else : 
+      out.re := UInt<1>(0)
+      out.im := UInt<1>(0)