diff options
| author | azidar | 2015-04-20 12:08:10 -0700 |
|---|---|---|
| committer | azidar | 2015-04-20 12:08:10 -0700 |
| commit | 7617e33993abf9f6be357e0261755a4736c2e085 (patch) | |
| tree | a8a32a3e0d731b49173f1c6f02056aea20902ada /test/chisel3/ComplexAssign.fir | |
| parent | 130c6676418e85d5d4dd12a0f0845e912eda8c3e (diff) | |
Fixed tests to use new execution arguments. Added and fixed chisel3 bugs
Diffstat (limited to 'test/chisel3/ComplexAssign.fir')
| -rw-r--r-- | test/chisel3/ComplexAssign.fir | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir deleted file mode 100644 index 14cb063c..00000000 --- a/test/chisel3/ComplexAssign.fir +++ /dev/null @@ -1,18 +0,0 @@ -;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s -;CHECK: To Flo -circuit ComplexAssign : - module ComplexAssign : - input in : {re : UInt(10), im : UInt(10)} - output out : {re : UInt(10), im : UInt(10)} - input e : UInt(1) - when e : - wire T_19 : {re : UInt(10), im : UInt(10)} - T_19 := in - out.re := T_19.re - out.im := T_19.im - else : - node T_20 = UInt(0, 1) - out.re := T_20 - node T_21 = UInt(0, 1) - out.im := T_21 -;CHECK: Finished To Flo |