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| author | Howard Mao | 2016-08-25 16:24:28 -0700 |
|---|---|---|
| committer | Howard Mao | 2016-08-25 16:24:28 -0700 |
| commit | e69d44fc944b5d93c852d54911ce7cf61abb6dd1 (patch) | |
| tree | 07347e35450f263018bd7a1ad5f9c8e0aa507bbf /src | |
| parent | 87ad4220c2eba50fb1ccc854b20021776c6d34de (diff) | |
update verilog generation test
Diffstat (limited to 'src')
| -rw-r--r-- | src/test/scala/firrtlTests/CompilerTests.scala | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala index da267588..5b154327 100644 --- a/src/test/scala/firrtlTests/CompilerTests.scala +++ b/src/test/scala/firrtlTests/CompilerTests.scala @@ -106,6 +106,16 @@ circuit Top : b <= a """ val check = Seq( + "`ifdef RANDOMIZE_ASSIGN", + "`define RANDOMIZE", + "`endif", + "`ifdef RANDOMIZE_REG_INIT", + "`define RANDOMIZE", + "`endif", + "`ifdef RANDOMIZE_MEM_INIT", + "`define RANDOMIZE", + "`endif", + "", "module Top(", " input a_0,", " input a_1,", |