From e69d44fc944b5d93c852d54911ce7cf61abb6dd1 Mon Sep 17 00:00:00 2001
From: Howard Mao
Date: Thu, 25 Aug 2016 16:24:28 -0700
Subject: update verilog generation test

---
 src/test/scala/firrtlTests/CompilerTests.scala | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'src')

diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index da267588..5b154327 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -106,6 +106,16 @@ circuit Top :
     b <= a
 """
    val check = Seq(
+      "`ifdef RANDOMIZE_ASSIGN",
+      "`define RANDOMIZE",
+      "`endif",
+      "`ifdef RANDOMIZE_REG_INIT",
+      "`define RANDOMIZE",
+      "`endif",
+      "`ifdef RANDOMIZE_MEM_INIT",
+      "`define RANDOMIZE",
+      "`endif",
+      "",
       "module Top(",
       "  input   a_0,",
       "  input   a_1,",
-- 
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