Run CheckHighForm after all non-emitter transforms in firrtl tests (#548)

* Run CheckHighForm after all non-emitter transforms in firrtl tests

* Remove shlw from checks.scala

* Removed mistake in fix

* Fix FirrtlSpec fix

2 files changed, 13 insertions, 4 deletions

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 457940d7..1268a149 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -76,7 +76,7 @@ object CheckHighForm extends Pass {
 
       e.op match {
         case Add | Sub | Mul | Div | Rem | Lt | Leq | Gt | Geq |
-             Eq | Neq | Dshl | Dshr | And | Or | Xor | Cat =>
+             Eq | Neq | Dshl | Dshr | And | Or | Xor | Cat | Dshlw =>
           correctNum(Option(2), 0)
         case AsUInt | AsSInt | AsClock | AsAsyncReset | Cvt | Neq | Not =>
           correctNum(Option(1), 0)
diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala
index b3729f96..c3c25cd5 100644
--- a/src/test/scala/firrtlTests/FirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/FirrtlSpec.scala
@@ -18,12 +18,21 @@ import firrtl.analyses.{GetNamespace, InstanceGraph, ModuleNamespaceAnnotation}
 import firrtl.annotations._
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation, RenameModules}
 import firrtl.util.BackendCompilationUtilities
-
 import scala.collection.mutable
 
+class CheckLowForm extends SeqTransform {
+  def inputForm = LowForm
+  def outputForm = LowForm
+  def transforms = Seq(
+    passes.CheckHighForm
+  )
+}
+
 trait FirrtlRunners extends BackendCompilationUtilities {
 
   val cppHarnessResourceName: String = "/firrtl/testTop.cpp"
+  /** Extra transforms to run by default */
+  val extraCheckTransforms = Seq(new CheckLowForm)
 
   private class RenameTop(newTopPrefix: String) extends Transform {
     def inputForm: LowForm.type = LowForm
@@ -85,7 +94,7 @@ trait FirrtlRunners extends BackendCompilationUtilities {
   def compileToVerilog(input: String, annotations: AnnotationSeq = Seq.empty): String = {
     val circuit = Parser.parse(input.split("\n").toIterator)
     val compiler = new VerilogCompiler
-    val res = compiler.compileAndEmit(CircuitState(circuit, HighForm, annotations))
+    val res = compiler.compileAndEmit(CircuitState(circuit, HighForm, annotations), extraCheckTransforms)
     res.getEmittedCircuit.value
   }
   /** Compile a Firrtl file
@@ -106,7 +115,7 @@ trait FirrtlRunners extends BackendCompilationUtilities {
       commonOptions = CommonOptions(topName = prefix, targetDirName = testDir.getPath)
       firrtlOptions = FirrtlExecutionOptions(
                         infoModeName = "ignore",
-                        customTransforms = customTransforms,
+                        customTransforms = customTransforms ++ extraCheckTransforms,
                         annotations = annotations.toList)
     }
     firrtl.Driver.execute(optionsManager)