Detect and error on registers with flip in type (#1031)

2 files changed, 28 insertions, 8 deletions

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index b6855d75..457940d7 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -25,6 +25,8 @@ object CheckHighForm extends Pass {
     s"$info: [module $mname] Poison $name cannot be a bundle type with flips.")
   class MemWithFlipException(info: Info, mname: String, name: String) extends PassException(
     s"$info: [module $mname] Memory $name cannot be a bundle type with flips.")
+  class RegWithFlipException(info: Info, mname: String, name: String) extends PassException(
+    s"$info: [module $mname] Register $name cannot be a bundle type with flips.")
   class InvalidAccessException(info: Info, mname: String) extends PassException(
     s"$info: [module $mname] Invalid access to non-reference.")
   class ModuleNotDefinedException(info: Info, mname: String, name: String) extends PassException(
@@ -166,13 +168,11 @@ object CheckHighForm extends Pass {
       val info = get_info(s) match {case NoInfo => minfo case x => x}
       s foreach checkName(info, mname, names)
       s match {
-        case DefRegister(info, name, _,_, reset, init) if reset.tpe == AsyncResetType =>
-          init match {
-            case _: Literal => // okay
-            case nonlit =>
-              val e = new NonLiteralAsyncResetValueException(info, mname, name, nonlit.serialize)
-              errors.append(e)
-          }
+        case DefRegister(info, name, tpe, _, reset, init) =>
+          if (hasFlip(tpe))
+            errors.append(new RegWithFlipException(info, mname, name))
+          if (reset.tpe == AsyncResetType && !init.isInstanceOf[Literal])
+            errors.append(new NonLiteralAsyncResetValueException(info, mname, name, init.serialize))
         case sx: DefMemory =>
           if (hasFlip(sx.dataType))
             errors.append(new MemWithFlipException(info, mname, sx.name))
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 3e6b19f9..af16ec03 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -10,7 +10,7 @@ import firrtl.ir.Circuit
 import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassException,InferWidths,CheckWidths,ResolveGenders,CheckGenders}
 
 class CheckSpec extends FlatSpec with Matchers {
-  "Connecting bundles of different types" should "throw an exception" in {
+  "Memories with flip in the data type" should "throw an exception" in {
     val passes = Seq(
       ToWorkingIR,
       CheckHighForm)
@@ -28,6 +28,26 @@ class CheckSpec extends FlatSpec with Matchers {
       }
     }
   }
+
+  "Registers with flip in the type" should "throw an exception" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input clk : Clock
+        |    input in : UInt<32>
+        |    output out : UInt<32>
+        |    reg r : {a : UInt<32>, flip b : UInt<32>}, clk
+        |    out <= in""".stripMargin
+    intercept[CheckHighForm.RegWithFlipException] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+
   "Instance loops a -> b -> a" should "be detected" in {
     val passes = Seq(
       ToWorkingIR,