diff options
| author | Albert Magyar | 2020-03-16 11:22:04 -0700 |
|---|---|---|
| committer | GitHub | 2020-03-16 11:22:04 -0700 |
| commit | d0500b33167cad060a9325d68b939d41279f6c9c (patch) | |
| tree | 19e29be01e09822c44473d3184277ed24b3158f9 /src | |
| parent | 44f0112c7a9d9e9fa7f87fa6e5f68916e76a3b19 (diff) | |
| parent | e41936d5283ba8caae2a23602e8e1a2baea391cb (diff) | |
Merge pull request #1437 from freechipsproject/name-conflicts
Check for name collisions of Modules
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/Checks.scala | 15 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/CheckSpec.scala | 43 |
2 files changed, 58 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index e176bcc4..3c9a7eda 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -33,6 +33,10 @@ trait CheckHighFormLike { this: Pass => s"$info: [module $mname] Register $name cannot be a bundle type with flips.") class InvalidAccessException(info: Info, mname: String) extends PassException( s"$info: [module $mname] Invalid access to non-reference.") + class ModuleNameNotUniqueException(info: Info, mname: String) extends PassException( + s"$info: Repeat definition of module $mname") + class DefnameConflictException(info: Info, mname: String, defname: String) extends PassException( + s"$info: defname $defname of extmodule $mname conflicts with an existing module") class ModuleNotDefinedException(info: Info, mname: String, name: String) extends PassException( s"$info: Module $name is not defined.") class IncorrectNumArgsException(info: Info, mname: String, op: String, n: Int) extends PassException( @@ -73,6 +77,17 @@ trait CheckHighFormLike { this: Pass => val moduleGraph = new ModuleGraph val moduleNames = (c.modules map (_.name)).toSet + val intModuleNames = c.modules.view.collect({ case m: Module => m.name }).toSet + + c.modules.view.groupBy(_.name).filter(_._2.length > 1).flatMap(_._2).foreach { + m => errors.append(new ModuleNameNotUniqueException(m.info, m.name)) + } + + c.modules.collect { + case ExtModule(info, name, _, defname, _) if (intModuleNames.contains(defname)) => + errors.append(new DefnameConflictException(info, name, defname)) + } + def checkHighFormPrimop(info: Info, mname: String, e: DoPrim): Unit = { def correctNum(ne: Option[Int], nc: Int): Unit = { ne match { diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala index 9a384d21..aa154bab 100644 --- a/src/test/scala/firrtlTests/CheckSpec.scala +++ b/src/test/scala/firrtlTests/CheckSpec.scala @@ -307,6 +307,49 @@ class CheckSpec extends FlatSpec with Matchers { } } } + + s"Duplicate module names" should "throw an exception" in { + val input = + s"""|circuit bar : + | module bar : + | input i : UInt<8> + | output o : UInt<8> + | o <= i + | module dup : + | input i : UInt<8> + | output o : UInt<8> + | o <= i + | module dup : + | input i : UInt<8> + | output o : UInt<8> + | o <= not(i) + |""".stripMargin + assertThrows[CheckHighForm.ModuleNameNotUniqueException] { + try { + checkHighInput(input) + } catch { + case e: firrtl.passes.PassExceptions => throw e.exceptions.head + } + } + } + + s"Defnames that conflict with pure-FIRRTL module names" should "throw an exception" in { + val input = + s"""|circuit bar : + | module bar : + | input i : UInt<8> + | output o : UInt<8> + | o <= i + | extmodule dup : + | input i : UInt<8> + | output o : UInt<8> + | defname = bar + |""".stripMargin + assertThrows[CheckHighForm.DefnameConflictException] { + checkHighInput(input) + } + } + } object CheckSpec { |
