Merge pull request #1454 from freechipsproject/inline-invalidate-resolve-kinds

Make InlineInstances invalidate ResolveKinds

2 files changed, 33 insertions, 4 deletions

diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index fd001827..9ddbe92e 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -25,9 +25,11 @@ case class InlineAnnotation(target: Named) extends SingleTargetAnnotation[Named]
   * pass can infinitely recurse.
   */
 class InlineInstances extends Transform with RegisteredTransform {
-   def inputForm = LowForm
-   def outputForm = LowForm
-   private [firrtl] val inlineDelim: String = "_"
+  def inputForm = LowForm
+  def outputForm = LowForm
+  private [firrtl] val inlineDelim: String = "_"
+
+  override def invalidates(a: Transform): Boolean = a == ResolveKinds
 
   val options = Seq(
     new ShellOption[Seq[String]](
diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala
index 3e606667..320b187c 100644
--- a/src/test/scala/firrtlTests/InlineInstancesTests.scala
+++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala
@@ -2,9 +2,14 @@
 
 package firrtlTests
 
+import firrtl._
 import firrtl.annotations._
-import firrtl.passes.{InlineAnnotation, InlineInstances}
+import firrtl.passes.{InlineAnnotation, InlineInstances, ResolveKinds}
 import firrtl.transforms.NoCircuitDedupAnnotation
+import firrtl.stage.TransformManager
+import firrtl.options.Dependency
+
+import FirrtlCheckers._
 
 /**
  * Tests inline instances transformation
@@ -537,6 +542,28 @@ class InlineInstancesTests extends LowTransformSpec {
        )
      )
   }
+
+  "InlineInstances" should "properly invalidate ResolveKinds" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst i of Inline
+        |    i.a <= a
+        |    b <= i.b
+        |  module Inline :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    b <= a""".stripMargin
+
+    val state = CircuitState(parse(input), ChirrtlForm, Seq(inline("Inline")))
+    val manager = new TransformManager(Seq(Dependency[InlineInstances], Dependency(ResolveKinds)))
+    val result = manager.execute(state)
+
+    result shouldNot containTree { case WRef("i_a", _, PortKind, _) => true }
+    result should    containTree { case WRef("i_a", _, WireKind, _) => true }
+  }
 }
 
 // Execution driven tests for inlining modules