[RFC] Factor out common test classes; package them (#1412)

* Pull out common test utilities into a separate package

* Project a fat jar for test utilities

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

71 files changed, 89 insertions, 31 deletions

diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
index 1eea3671..46f36e87 100644
--- a/src/test/scala/firrtlTests/FirrtlSpec.scala
+++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package firrtlTests
+package firrtl.testutils
 
 import java.io._
 import java.security.Permission
diff --git a/src/test/scala/firrtlTests/PassTests.scala b/src/test/scala/firrtl/testutils/PassTests.scala
index 3d2bc249..c172163e 100644
--- a/src/test/scala/firrtlTests/PassTests.scala
+++ b/src/test/scala/firrtl/testutils/PassTests.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package firrtlTests
+package firrtl.testutils
 
 import org.scalatest.FlatSpec
 import firrtl.ir.Circuit
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index a1c6580d..8077d314 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -12,6 +12,7 @@ import firrtl.transforms.OptimizableExtModuleAnnotation
 import firrtl.passes.InlineAnnotation
 import firrtl.passes.memlib.PinAnnotation
 import firrtl.util.BackendCompilationUtilities
+import firrtl.testutils._
 import net.jcazevedo.moultingyaml._
 import org.scalatest.Matchers
 
diff --git a/src/test/scala/firrtlTests/AsyncResetSpec.scala b/src/test/scala/firrtlTests/AsyncResetSpec.scala
index ebc94cc8..c0c79165 100644
--- a/src/test/scala/firrtlTests/AsyncResetSpec.scala
+++ b/src/test/scala/firrtlTests/AsyncResetSpec.scala
@@ -3,6 +3,7 @@
 package firrtlTests
 
 import firrtl._
+import firrtl.testutils._
 import FirrtlCheckers._
 
 class AsyncResetSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index 1a5341e0..e4acc735 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -5,6 +5,7 @@ package firrtlTests
 import firrtl._
 import firrtl.ir.Circuit
 import firrtl.passes._
+import firrtl.testutils._
 
 class InoutVerilogSpec extends FirrtlFlatSpec {
 
diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala
index 715e0cda..6c9d4047 100644
--- a/src/test/scala/firrtlTests/CInferMDirSpec.scala
+++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala
@@ -6,6 +6,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.passes._
 import firrtl.transforms._
+import firrtl.testutils._
 
 class CInferMDirSpec extends LowTransformSpec {
   object CInferMDirCheckPass extends Pass {
diff --git a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
index 2ff40282..6f34ceba 100644
--- a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
+++ b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl._
 import firrtl.transforms._
+import firrtl.testutils._
 import annotations._
 import java.io.File
 import java.nio.file.Paths
diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
index cc3ed49f..34e0da03 100644
--- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala
+++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl.{CircuitState, UnknownForm, Transform}
 import firrtl.passes._
+import firrtl.testutils._
 
 class CheckInitializationSpec extends FirrtlFlatSpec {
   private val passes = Seq(
diff --git a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
index 25ce8742..3868c237 100644
--- a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
@@ -7,8 +7,9 @@ import firrtl.ir._
 import firrtl.passes._
 import firrtl.transforms._
 import firrtl.Mappers._
-import FirrtlCheckers._
 import firrtl.PrimOps.AsClock
+import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers._
 
 class ChirrtlMemSpec extends LowTransformSpec {
   object MemEnableCheckPass extends Pass {
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index b82637b6..dcc8b872 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl._
 import firrtl.passes._
+import firrtl.testutils._
 
 class ChirrtlSpec extends FirrtlFlatSpec {
   def transforms = Seq(
diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala
index a30416b3..9233d4d5 100644
--- a/src/test/scala/firrtlTests/ClockListTests.scala
+++ b/src/test/scala/firrtlTests/ClockListTests.scala
@@ -6,6 +6,7 @@ import java.io._
 import firrtl._
 import firrtl.ir.Circuit
 import firrtl.passes._
+import firrtl.testutils._
 import clocklist._
 
 class ClockListTests extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/CompilerUtilsSpec.scala b/src/test/scala/firrtlTests/CompilerUtilsSpec.scala
index 1d349db1..bfb53ce1 100644
--- a/src/test/scala/firrtlTests/CompilerUtilsSpec.scala
+++ b/src/test/scala/firrtlTests/CompilerUtilsSpec.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl._
 import firrtl.CompilerUtils.mergeTransforms
+import firrtl.testutils._
 
 class CompilerUtilsSpec extends FirrtlFlatSpec {
 
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 3296b13b..bb7fde41 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -5,6 +5,7 @@ package firrtlTests
 import firrtl._
 import firrtl.passes._
 import firrtl.transforms._
+import firrtl.testutils._
 import firrtl.annotations.Annotation
 
 class ConstantPropagationSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index 809f2b1e..f1b2045e 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -6,10 +6,13 @@ import firrtl.ir.Circuit
 import firrtl._
 import firrtl.passes.Pass
 import firrtl.ir._
+
 import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, RunFirrtlTransformAnnotation}
 import firrtl.options.Dependency
 import firrtl.transforms.IdentityTransform
 
+import firrtl.testutils._
+
 import scala.reflect.runtime
 
 object CustomTransformSpec {
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index bfd47042..93934c93 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -7,6 +7,7 @@ import firrtl.passes._
 import firrtl.transforms._
 import firrtl.annotations._
 import firrtl.passes.memlib.SimpleTransform
+import firrtl.testutils._
 
 import java.io.File
 import java.nio.file.Paths
diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala
index d55b7462..f59ccb2c 100644
--- a/src/test/scala/firrtlTests/DriverSpec.scala
+++ b/src/test/scala/firrtlTests/DriverSpec.scala
@@ -12,6 +12,7 @@ import firrtl._
 import firrtl.FileUtils
 import firrtl.annotations._
 import firrtl.util.BackendCompilationUtilities
+import firrtl.testutils.FirrtlFlatSpec
 
 import scala.util.Success
 
diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
index f7e694f3..d4b3d0df 100644
--- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala
+++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl._
 import firrtl.passes._
+import firrtl.testutils._
 
 class ExpandWhensSpec extends FirrtlFlatSpec {
   private val transforms = Seq(
diff --git a/src/test/scala/firrtlTests/ExtModuleSpec.scala b/src/test/scala/firrtlTests/ExtModuleSpec.scala
index 96668222..7379f1aa 100644
--- a/src/test/scala/firrtlTests/ExtModuleSpec.scala
+++ b/src/test/scala/firrtlTests/ExtModuleSpec.scala
@@ -2,6 +2,8 @@
 
 package firrtlTests
 
+import firrtl.testutils._
+
 class SimpleExtModuleExecutionTest extends ExecutionTest("SimpleExtModuleTester", "/blackboxes",
                                                          Seq("SimpleExtModule"))
 class MultiExtModuleExecutionTest extends ExecutionTest("MultiExtModuleTester", "/blackboxes",
diff --git a/src/test/scala/firrtlTests/ExtModuleTests.scala b/src/test/scala/firrtlTests/ExtModuleTests.scala
index 207dc29e..9ab3429e 100644
--- a/src/test/scala/firrtlTests/ExtModuleTests.scala
+++ b/src/test/scala/firrtlTests/ExtModuleTests.scala
@@ -2,6 +2,8 @@
 
 package firrtlTests
 
+import firrtl.testutils._
+
 class ExtModuleTests extends FirrtlFlatSpec {
   "extmodule" should "serialize and re-parse equivalently" in {
     val input =
diff --git a/src/test/scala/firrtlTests/FeatureSpec.scala b/src/test/scala/firrtlTests/FeatureSpec.scala
index bdc61b14..c7c8f4ac 100644
--- a/src/test/scala/firrtlTests/FeatureSpec.scala
+++ b/src/test/scala/firrtlTests/FeatureSpec.scala
@@ -2,6 +2,8 @@
 
 package firrtlTests
 
+import firrtl.testutils.ExecutionTest
+
 // Miscellaneous Feature Checks
 class NestedSubAccessExecutionTest extends ExecutionTest("NestedSubAccessTester", "/features")
 
diff --git a/src/test/scala/firrtlTests/FlattenTests.scala b/src/test/scala/firrtlTests/FlattenTests.scala
index 19de9433..34edfe58 100644
--- a/src/test/scala/firrtlTests/FlattenTests.scala
+++ b/src/test/scala/firrtlTests/FlattenTests.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName}
 import firrtl.transforms.{FlattenAnnotation, Flatten, NoCircuitDedupAnnotation}
+import firrtl.testutils._
 
 /**
  * Tests deep inline transformation
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
index f2885fdf..9913a7c1 100644
--- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala
+++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
@@ -5,7 +5,8 @@ package firrtlTests
 import firrtl._
 import firrtl.ir._
 import firrtl.passes._
-import FirrtlCheckers._
+import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers._
 
 class InferReadWriteSpec extends SimpleTransformSpec {
   class InferReadWriteCheckException extends PassException(
diff --git a/src/test/scala/firrtlTests/InferResetsSpec.scala b/src/test/scala/firrtlTests/InferResetsSpec.scala
index 0bcc459c..b607fb46 100644
--- a/src/test/scala/firrtlTests/InferResetsSpec.scala
+++ b/src/test/scala/firrtlTests/InferResetsSpec.scala
@@ -6,7 +6,8 @@ import firrtl._
 import firrtl.ir._
 import firrtl.passes.{CheckHighForm, CheckTypes, CheckInitialization}
 import firrtl.transforms.{CheckCombLoops, InferResets}
-import FirrtlCheckers._
+import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers._
 
 // TODO
 // - Test nodes in the connection
diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala
index 9d6206af..0a95b462 100644
--- a/src/test/scala/firrtlTests/InfoSpec.scala
+++ b/src/test/scala/firrtlTests/InfoSpec.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl._
 import firrtl.ir._
+import firrtl.testutils._
 import FirrtlCheckers._
 
 class InfoSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala
index 320b187c..27102785 100644
--- a/src/test/scala/firrtlTests/InlineInstancesTests.scala
+++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala
@@ -6,11 +6,11 @@ import firrtl._
 import firrtl.annotations._
 import firrtl.passes.{InlineAnnotation, InlineInstances, ResolveKinds}
 import firrtl.transforms.NoCircuitDedupAnnotation
+import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers._
 import firrtl.stage.TransformManager
 import firrtl.options.Dependency
 
-import FirrtlCheckers._
-
 /**
  * Tests inline instances transformation
  */
diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala
index 96703fc0..352a5e52 100644
--- a/src/test/scala/firrtlTests/IntegrationSpec.scala
+++ b/src/test/scala/firrtlTests/IntegrationSpec.scala
@@ -3,6 +3,7 @@
 package firrtlTests
 
 import firrtl._
+import firrtl.testutils._
 
 import java.io.File
 
diff --git a/src/test/scala/firrtlTests/LegalizeSpec.scala b/src/test/scala/firrtlTests/LegalizeSpec.scala
index acc88619..22fef730 100644
--- a/src/test/scala/firrtlTests/LegalizeSpec.scala
+++ b/src/test/scala/firrtlTests/LegalizeSpec.scala
@@ -2,5 +2,7 @@
 
 package firrtlTests
 
+import firrtl.testutils.ExecutionTest
+
 class LegalizeExecutionTest extends ExecutionTest("Legalize", "/passes/Legalize")
 
diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala
index b0e5727b..4e8a7fa5 100644
--- a/src/test/scala/firrtlTests/LowerTypesSpec.scala
+++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala
@@ -6,6 +6,7 @@ import firrtl.Parser
 import firrtl.passes._
 import firrtl.transforms._
 import firrtl._
+import firrtl.testutils._
 
 class LowerTypesSpec extends FirrtlFlatSpec {
   private def transforms = Seq(
diff --git a/src/test/scala/firrtlTests/MemEnFeedbackSpec.scala b/src/test/scala/firrtlTests/MemEnFeedbackSpec.scala
index d94d199a..0f01ca25 100644
--- a/src/test/scala/firrtlTests/MemEnFeedbackSpec.scala
+++ b/src/test/scala/firrtlTests/MemEnFeedbackSpec.scala
@@ -3,6 +3,7 @@
 package firrtlTests
 
 import firrtl._
+import firrtl.testutils.FirrtlFlatSpec
 
 // Tests long-standing bug from #1179, VerilogMemDelays producing combinational loops in corner case
 abstract class MemEnFeedbackSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/MemSpec.scala b/src/test/scala/firrtlTests/MemSpec.scala
index 612a952d..c7ab8db7 100644
--- a/src/test/scala/firrtlTests/MemSpec.scala
+++ b/src/test/scala/firrtlTests/MemSpec.scala
@@ -3,6 +3,7 @@
 package firrtlTests
 
 import firrtl._
+import firrtl.testutils._
 import FirrtlCheckers._
 
 class MemSpec extends FirrtlPropSpec with FirrtlMatchers {
diff --git a/src/test/scala/firrtlTests/MultiThreadingSpec.scala b/src/test/scala/firrtlTests/MultiThreadingSpec.scala
index 72c66e93..e41e6835 100644
--- a/src/test/scala/firrtlTests/MultiThreadingSpec.scala
+++ b/src/test/scala/firrtlTests/MultiThreadingSpec.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl.FileUtils
 import firrtl.{ChirrtlForm, CircuitState}
+import firrtl.testutils._
 
 import scala.concurrent.duration.Duration
 import scala.concurrent.{Await, ExecutionContext, Future}
diff --git a/src/test/scala/firrtlTests/NamespaceSpec.scala b/src/test/scala/firrtlTests/NamespaceSpec.scala
index 8aa29705..a9bb844d 100644
--- a/src/test/scala/firrtlTests/NamespaceSpec.scala
+++ b/src/test/scala/firrtlTests/NamespaceSpec.scala
@@ -3,6 +3,7 @@
 package firrtlTests
 
 import firrtl.Namespace
+import firrtl.testutils._
 
 class NamespaceSpec extends FirrtlFlatSpec {
 
diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala
index 4f28e100..3958bfad 100644
--- a/src/test/scala/firrtlTests/ParserSpec.scala
+++ b/src/test/scala/firrtlTests/ParserSpec.scala
@@ -3,6 +3,7 @@
 package firrtlTests
 
 import firrtl._
+import firrtl.testutils._
 import org.scalacheck.Gen
 
 class ParserSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/PresetSpec.scala b/src/test/scala/firrtlTests/PresetSpec.scala
index d35aa69f..689a910d 100644
--- a/src/test/scala/firrtlTests/PresetSpec.scala
+++ b/src/test/scala/firrtlTests/PresetSpec.scala
@@ -3,8 +3,9 @@
 package firrtlTests
 
 import firrtl._
-import FirrtlCheckers._
 import firrtl.annotations._
+import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers._
 
 class PresetSpec extends FirrtlFlatSpec {
   type Mod = Seq[String]
diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala
index 7f41fb26..743e00ef 100644
--- a/src/test/scala/firrtlTests/ProtoBufSpec.scala
+++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala
@@ -5,6 +5,7 @@ package firrtlTests
 import firrtl.FirrtlProtos.Firrtl
 import firrtl._
 import firrtl.ir._
+import firrtl.testutils._
 
 class ProtoBufSpec extends FirrtlFlatSpec {
 
diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
index 1e578973..dd3155d0 100644
--- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala
+++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
@@ -5,6 +5,7 @@ package firrtlTests
 import firrtl._
 import firrtl.ir._
 import firrtl.Mappers._
+import firrtl.testutils._
 
 import collection.mutable
 
diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/RenameMapSpec.scala
index dc091b0a..d0c68eba 100644
--- a/src/test/scala/firrtlTests/RenameMapSpec.scala
+++ b/src/test/scala/firrtlTests/RenameMapSpec.scala
@@ -5,6 +5,7 @@ package firrtlTests
 import firrtl.RenameMap
 import firrtl.RenameMap.IllegalRenameException
 import firrtl.annotations._
+import firrtl.testutils._
 
 class RenameMapSpec extends FirrtlFlatSpec {
   val cir   = CircuitTarget("Top")
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index 72171d43..cd2fdb05 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -8,6 +8,7 @@ import firrtl.passes._
 import firrtl.transforms._
 import firrtl.passes.memlib._
 import firrtl.FileUtils
+import firrtl.testutils._
 import annotations._
 import FirrtlCheckers._
 
diff --git a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala
index 5b1e39dc..fcf36876 100644
--- a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala
+++ b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl._
 import firrtl.passes._
+import firrtl.testutils._
 
 class ReplaceAccessesSpec extends FirrtlFlatSpec {
   val transforms = Seq(
diff --git a/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala b/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala
index 01adca3a..b3c98e88 100644
--- a/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala
+++ b/src/test/scala/firrtlTests/ReplaceTruncatingArithmeticSpec.scala
@@ -3,7 +3,8 @@
 package firrtlTests
 
 import firrtl._
-import FirrtlCheckers._
+import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers._
 
 class ReplaceTruncatingArithmeticSpec extends FirrtlFlatSpec {
   def compile(input: String): CircuitState =
diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala
index 826343cf..30535466 100644
--- a/src/test/scala/firrtlTests/StringSpec.scala
+++ b/src/test/scala/firrtlTests/StringSpec.scala
@@ -3,6 +3,7 @@
 package firrtlTests
 
 import firrtl.ir.StringLit
+import firrtl.testutils._
 
 import java.io._
 
diff --git a/src/test/scala/firrtlTests/UniquifySpec.scala b/src/test/scala/firrtlTests/UniquifySpec.scala
index 38063e5c..074da256 100644
--- a/src/test/scala/firrtlTests/UniquifySpec.scala
+++ b/src/test/scala/firrtlTests/UniquifySpec.scala
@@ -9,6 +9,7 @@ import firrtl.annotations._
 import firrtl.annotations.TargetToken._
 import firrtl.transforms.DontTouchAnnotation
 import firrtl.util.TestOptions
+import firrtl.testutils._
 
 class UniquifySpec extends FirrtlFlatSpec {
 
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 8788bac7..288bf336 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -7,6 +7,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.passes._
 import firrtl.transforms._
+import firrtl.testutils._
 import FirrtlCheckers._
 
 class UnitTests extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 825d706f..46661595 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -6,8 +6,9 @@ import firrtl._
 import firrtl.annotations._
 import firrtl.passes._
 import firrtl.transforms.VerilogRename
-import FirrtlCheckers._
 import firrtl.transforms.CombineCats
+import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers._
 
 class DoPrimVerilog extends FirrtlFlatSpec {
   "Xorr" should "emit correctly" in {
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 64afe12b..c5e3834e 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl._
 import firrtl.passes._
+import firrtl.testutils._
 
 class WidthSpec extends FirrtlFlatSpec {
   private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = {
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index 3ec412d2..48089f0c 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl._
 import firrtl.passes._
+import firrtl.testutils._
 import annotations._
 import wiring._
 
diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index b7f16034..b53f55ea 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -4,6 +4,7 @@ package firrtlTests
 
 import firrtl._
 import firrtl.passes._
+import firrtl.testutils._
 
 class ZeroWidthTests extends FirrtlFlatSpec {
   def transforms = Seq(
diff --git a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
index 8f748732..a0d444b3 100644
--- a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
+++ b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
@@ -5,7 +5,7 @@ import firrtl.analyses.InstanceGraph
 import firrtl.graph.DiGraph
 import firrtl.WDefInstance
 import firrtl.passes._
-import firrtlTests._
+import firrtl.testutils._
 
 class InstanceGraphTests extends FirrtlFlatSpec {
   private def getEdgeSet(graph: DiGraph[String]): collection.Map[String, collection.Set[String]] = {
diff --git a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
index 11c40d5f..5b610890 100644
--- a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
@@ -7,7 +7,7 @@ import firrtl.annotations._
 import firrtl.annotations.analysis.DuplicationHelper
 import firrtl.annotations.transforms.NoSuchTargetException
 import firrtl.transforms.DontTouchAnnotation
-import firrtlTests.{FirrtlMatchers, FirrtlPropSpec}
+import firrtl.testutils.{FirrtlMatchers, FirrtlPropSpec}
 
 class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
   val input =
diff --git a/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala
index ea4127bc..cbcd72e9 100644
--- a/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala
@@ -3,13 +3,15 @@
 package firrtlTests
 package annotationTests
 
-import firrtlTests._
 import firrtl._
+import firrtl.testutils.FirrtlFlatSpec
+
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
 
 case object FoundTargetDirTransformRanAnnotation extends NoTargetAnnotation
 case object FoundTargetDirTransformFoundTargetDirAnnotation extends NoTargetAnnotation
 
+
 /** Looks for [[TargetDirAnnotation]] */
 class FindTargetDirTransform extends Transform {
   def inputForm = HighForm
diff --git a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
index 1bc4c927..641eeb99 100644
--- a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
@@ -4,7 +4,7 @@ package firrtlTests.annotationTests
 
 import firrtl.annotations.{CircuitTarget, GenericTarget, ModuleTarget, Target}
 import firrtl.annotations.TargetToken._
-import firrtlTests.FirrtlPropSpec
+import firrtl.testutils.FirrtlPropSpec
 
 class TargetSpec extends FirrtlPropSpec {
   def check(comp: Target): Unit = {
diff --git a/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala b/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala
index 5abeb819..2654f476 100644
--- a/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala
+++ b/src/test/scala/firrtlTests/execution/SimpleExecutionTest.scala
@@ -3,7 +3,7 @@ package firrtlTests.execution
 import java.io.File
 
 import firrtl.ir._
-import firrtlTests._
+import firrtl.testutils._
 
 sealed trait SimpleTestCommand
 case class Step(n: Int) extends SimpleTestCommand
diff --git a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala
index e1b03728..c4de1f46 100644
--- a/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedPointMathSpec.scala
@@ -3,7 +3,7 @@
 package firrtlTests.fixed
 
 import firrtl.{CircuitState, ChirrtlForm, LowFirrtlCompiler}
-import firrtlTests.FirrtlFlatSpec
+import firrtl.testutils.FirrtlFlatSpec
 
 class FixedPointMathSpec extends FirrtlFlatSpec {
 
diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index baf1cda7..1a7092bb 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -5,6 +5,7 @@ package fixed
 
 import firrtl._
 import firrtl.passes._
+import firrtl.testutils._
 
 class FixedTypeInferenceSpec extends FirrtlFlatSpec {
   private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = {
diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
index 30c606d2..9dc61927 100644
--- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
@@ -5,6 +5,7 @@ package fixed
 
 import firrtl._
 import firrtl.passes._
+import firrtl.testutils._
 
 class RemoveFixedTypeSpec extends FirrtlFlatSpec {
   private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = {
diff --git a/src/test/scala/firrtlTests/graph/DiGraphTests.scala b/src/test/scala/firrtlTests/graph/DiGraphTests.scala
index 0771460b..71cc517e 100644
--- a/src/test/scala/firrtlTests/graph/DiGraphTests.scala
+++ b/src/test/scala/firrtlTests/graph/DiGraphTests.scala
@@ -3,7 +3,7 @@
 package firrtlTests.graph
 
 import firrtl.graph._
-import firrtlTests._
+import firrtl.testutils._
 
 //scalastyle:off magic.number
 class DiGraphTests extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/graph/EulerTourTests.scala b/src/test/scala/firrtlTests/graph/EulerTourTests.scala
index 0b69ce61..f6deb721 100644
--- a/src/test/scala/firrtlTests/graph/EulerTourTests.scala
+++ b/src/test/scala/firrtlTests/graph/EulerTourTests.scala
@@ -1,7 +1,7 @@
 package firrtlTests.graph
 
 import firrtl.graph._
-import firrtlTests._
+import firrtl.testutils._
 
 class EulerTourTests extends FirrtlFlatSpec {
 
diff --git a/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala b/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala
index f72fc292..eeb70286 100644
--- a/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala
+++ b/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala
@@ -7,7 +7,7 @@ import firrtl.{ChirrtlForm, CircuitState, LowFirrtlCompiler}
 import firrtl.ir._
 
 import firrtl.constraint._
-import firrtlTests.FirrtlFlatSpec
+import firrtl.testutils.FirrtlFlatSpec
 
 class IntervalMathSpec extends FirrtlFlatSpec {
   val SumPattern         = """.*output sum.*<(\d+)>.*""".r
diff --git a/src/test/scala/firrtlTests/interval/IntervalSpec.scala b/src/test/scala/firrtlTests/interval/IntervalSpec.scala
index 056b0419..3914aba0 100644
--- a/src/test/scala/firrtlTests/interval/IntervalSpec.scala
+++ b/src/test/scala/firrtlTests/interval/IntervalSpec.scala
@@ -6,6 +6,7 @@ import firrtl.ir.Circuit
 import firrtl.passes._
 import firrtl.passes.CheckTypes.InvalidConnect
 import firrtl.passes.CheckWidths.DisjointSqueeze
+import firrtl.testutils.FirrtlFlatSpec
 
 class IntervalSpec extends FirrtlFlatSpec {
   private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = {
diff --git a/src/test/scala/firrtlTests/options/OptionParserSpec.scala b/src/test/scala/firrtlTests/options/OptionParserSpec.scala
index 3059ba1a..1d055801 100644
--- a/src/test/scala/firrtlTests/options/OptionParserSpec.scala
+++ b/src/test/scala/firrtlTests/options/OptionParserSpec.scala
@@ -10,7 +10,7 @@ import scopt.OptionParser
 
 import org.scalatest.{FlatSpec, Matchers}
 
-class OptionParserSpec extends FlatSpec with Matchers with firrtlTests.Utils {
+class OptionParserSpec extends FlatSpec with Matchers with firrtl.testutils.Utils {
 
   case class IntAnnotation(x: Int) extends NoTargetAnnotation {
     def extract: Int = x
diff --git a/src/test/scala/firrtlTests/options/phases/GetIncludesSpec.scala b/src/test/scala/firrtlTests/options/phases/GetIncludesSpec.scala
index 3bdf65a8..defda6c0 100644
--- a/src/test/scala/firrtlTests/options/phases/GetIncludesSpec.scala
+++ b/src/test/scala/firrtlTests/options/phases/GetIncludesSpec.scala
@@ -19,7 +19,7 @@ case object C extends NoTargetAnnotation
 case object D extends NoTargetAnnotation
 case object E extends NoTargetAnnotation
 
-class GetIncludesSpec extends FlatSpec with Matchers with BackendCompilationUtilities with firrtlTests.Utils {
+class GetIncludesSpec extends FlatSpec with Matchers with BackendCompilationUtilities with firrtl.testutils.Utils {
 
   val dir = new File("test_run_dir/GetIncludesSpec")
   dir.mkdirs()
diff --git a/src/test/scala/firrtlTests/options/phases/WriteOutputAnnotationsSpec.scala b/src/test/scala/firrtlTests/options/phases/WriteOutputAnnotationsSpec.scala
index c5fc958c..176362cc 100644
--- a/src/test/scala/firrtlTests/options/phases/WriteOutputAnnotationsSpec.scala
+++ b/src/test/scala/firrtlTests/options/phases/WriteOutputAnnotationsSpec.scala
@@ -11,7 +11,7 @@ import firrtl.annotations.{DeletedAnnotation, NoTargetAnnotation}
 import firrtl.options.{InputAnnotationFileAnnotation, OutputAnnotationFileAnnotation, Phase, WriteDeletedAnnotation}
 import firrtl.options.phases.{GetIncludes, WriteOutputAnnotations}
 
-class WriteOutputAnnotationsSpec extends FlatSpec with Matchers with firrtlTests.Utils {
+class WriteOutputAnnotationsSpec extends FlatSpec with Matchers with firrtl.testutils.Utils {
 
   val dir = "test_run_dir/WriteOutputAnnotationSpec"
 
diff --git a/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala b/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala
index e6129550..39b25dc2 100644
--- a/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala
+++ b/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala
@@ -16,7 +16,7 @@ import firrtl.util.BackendCompilationUtilities
   * This test uses the [[org.scalatest.FeatureSpec FeatureSpec]] intentionally as this test exercises the top-level
   * interface and is more suitable to an Acceptance Testing style.
   */
-class FirrtlMainSpec extends FeatureSpec with GivenWhenThen with Matchers with firrtlTests.Utils
+class FirrtlMainSpec extends FeatureSpec with GivenWhenThen with Matchers with firrtl.testutils.Utils
     with BackendCompilationUtilities {
 
   /** Parameterizes one test of [[FirrtlMain]]. Running the [[FirrtlMain]] `main` with certain args should produce
diff --git a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
index feba5a24..2c746c99 100644
--- a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
@@ -5,8 +5,8 @@ package firrtlTests.transforms
 import firrtl.annotations.{CircuitName, ModuleName}
 import firrtl.transforms._
 import firrtl.{Transform, VerilogEmitter}
-import firrtlTests.LowTransformSpec
 import firrtl.FileUtils
+import firrtl.testutils.LowTransformSpec
 
 
 class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
diff --git a/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala b/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala
index 6ac2d14e..f2672bce 100644
--- a/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/CombineCatsSpec.scala
@@ -6,8 +6,8 @@ import firrtl.PrimOps._
 import firrtl._
 import firrtl.ir.DoPrim
 import firrtl.transforms.{CombineCats, MaxCatLenAnnotation}
-import firrtlTests.FirrtlFlatSpec
-import firrtlTests.FirrtlCheckers._
+import firrtl.testutils.FirrtlFlatSpec
+import firrtl.testutils.FirrtlCheckers._
 
 class CombineCatsSpec extends FirrtlFlatSpec {
   private val transforms = Seq(new IRToWorkingIR, new CombineCats)
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index 971e8a1d..c96517ad 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -6,6 +6,7 @@ package transforms
 import firrtl.RenameMap
 import firrtl.annotations._
 import firrtl.transforms.{DedupModules, NoCircuitDedupAnnotation}
+import firrtl.testutils._
 
 
 /**
diff --git a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
index b4ecf058..c280f134 100644
--- a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
@@ -5,6 +5,7 @@ import firrtl.annotations.{CircuitName, ComponentName, ModuleName}
 import firrtl.transforms.{GroupAnnotation, GroupComponents, NoCircuitDedupAnnotation}
 import firrtl._
 import firrtl.ir._
+import firrtl.testutils._
 
 import FirrtlCheckers._
 
diff --git a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
index 72b006ec..c5847364 100644
--- a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
@@ -2,7 +2,7 @@
 
 package firrtlTests.transforms
 
-import firrtlTests.FirrtlFlatSpec
+import firrtl.testutils.FirrtlFlatSpec
 import firrtl._
 import firrtl.passes._
 import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation}
diff --git a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
index 5c2412ae..d7c76167 100644
--- a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
+++ b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
@@ -3,8 +3,8 @@
 package firrtlTests.transforms
 
 import firrtl._
-import firrtlTests.FirrtlFlatSpec
-import firrtlTests.FirrtlCheckers._
+import firrtl.testutils._
+import firrtl.testutils.FirrtlCheckers.containLine
 
 class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
   def compile(input: String): CircuitState =
diff --git a/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala b/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
index b9d92a6a..9b020b8e 100644
--- a/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/RemoveResetSpec.scala
@@ -4,8 +4,8 @@ package firrtlTests.transforms
 
 import org.scalatest.GivenWhenThen
 
-import firrtlTests.FirrtlFlatSpec
-import firrtlTests.FirrtlCheckers._
+import firrtl.testutils.FirrtlFlatSpec
+import firrtl.testutils.FirrtlCheckers._
 
 import firrtl.{CircuitState, WRef}
 import firrtl.ir.{Connect, Mux}
diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
index 089f4a10..e26b0445 100644
--- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
+++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
@@ -15,6 +15,7 @@ import firrtl.annotations.{
    Target
 }
 import firrtl.transforms.TopWiring._
+import firrtl.testutils._
 
 
 trait TopWiringTestsCommon extends FirrtlRunners {