Added debug print statements to dump fields from nodes, and updated tests to call firrtl correctly to enable/disable them

5 files changed, 73 insertions, 20 deletions

diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 9ec4b666..259bba10 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -83,6 +83,9 @@ public defstruct DefInstance <: Stmt :
 public defstruct DefMemory <: Stmt :
    name: Symbol
    type: VectorType
+public defstruct DefNode <: Stmt :
+   name: Symbol
+   value: Expression
 public defstruct DefAccessor <: Stmt :
    name: Symbol
    source: Expression
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 8904bd27..fe940a9f 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -18,16 +18,20 @@ defpackage firrtl-main :
    import stanza.parser
    import firrtl.ir-utils
 
-public var PRINT-TYPES : True|False = false
+defn set-printvars! (p:List<Char>) :
+   if contains(p,'t') : PRINT-TYPES = true
+   if contains(p,'k') : PRINT-KINDS = true
+   if contains(p,'w') : PRINT-WIDTHS = true
+   if contains(p,'c') : PRINT-CIRCUITS = true
 
 defn main () :
    val arg = commandline-arguments()
    val args = split(arg,' ')
    val lexed = lex-file(args[1])
    val c = parse-firrtl(lexed)
-   ;println(c)
+   if length(args) >= 4 :
+      set-printvars!(to-list(args[3]))
    run-passes(c,to-list(args[2]))
 
 main()
 
-
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 176a812c..34dbcec7 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -112,6 +112,8 @@ rd.defsyntax firrtl :
          DefMemory(ut(name), type)
       (inst ?name:#symbol of ?module:#exp) :
          DefInstance(ut(name), module)
+      (node ?name:#symbol = ?exp:#exp) :
+         DefNode(ut(name), exp)
       (accessor ?name:#symbol = ?source:#exp (@get ?index:#exp)) :
          DefAccessor(ut(name), source, index)
       ((?body:#comm ...)) :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 7fe61ff2..1aaa264a 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -3,6 +3,10 @@ defpackage firrtl.ir-utils :
    import verse
    import firrtl.ir2
 
+;============== DEBUG STUFF =============================
+
+public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Element|Port) -> False
+
 ;============== PRINTERS ===================================
 defmethod print (o:OutputStream, d:Direction) :
    print{o, _} $
@@ -56,6 +60,7 @@ defmethod print (o:OutputStream, e:Expression) :
          print(o, ")")
       (e:ReadPort) : print-all(o, ["ReadPort(" mem(e) ", " index(e) ")"])
       (e:Null) : print-all(o, ["Null"])
+   print-debug(o,e)
 
 defmethod print (o:OutputStream, c:Stmt) :
    match(c) :
@@ -74,6 +79,8 @@ defmethod print (o:OutputStream, c:Stmt) :
          print-all(["mem " name(c) " : " type(c)])
       (c:DefInstance) :
          print-all(["inst " name(c) " of " module(c)])
+      (c:DefNode) :
+         print-all(["node " name(c) " = " value(c)])      
       (c:DefAccessor) :
          print-all(["accessor " name(c) " = " source(c) "[" index(c) "]"])      
       (c:Conditionally) :
@@ -88,6 +95,7 @@ defmethod print (o:OutputStream, c:Stmt) :
          print-all(o, [loc(c) " := " exp(c)])
       (c:EmptyStmt) :
          print(o, "skip")
+   print-debug(o,c)
 
 defmethod print (o:OutputStream, e:Element) :
    match(e) :
@@ -103,6 +111,7 @@ defmethod print (o:OutputStream, e:Element) :
          print-all(o, ["Instance(" module(e) ", "])
          print-all(o, join(ports(e), ", "))
          print(o, ")")
+   print-debug(o,e)
 
 defmethod print (o:OutputStream, p:WritePort) :
    print-all(o, [index(p) " => WritePort(" value(p) ", " enable(p) ")"])
@@ -123,9 +132,11 @@ defmethod print (o:OutputStream, t:Type) :
          print(o, "}")
       (t:VectorType) :
          print-all(o, [type(t) "[" size(t) "]"])
+   print-debug(o,t)
 
 defmethod print (o:OutputStream, p:Port) :
    print-all(o, [direction(p) " " name(p) " : " type(p)])
+   print-debug(o,p)
 
 defmethod print (o:OutputStream, m:Module) :
    println-all(o, ["module " name(m) " :"])
@@ -207,6 +218,7 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
                            key(entry) => map(f, value(entry))
          LetRec(entries*, body(c))                  
       (c:DefAccessor) : DefAccessor(name(c), f(source(c)), f(index(c)))
+      (c:DefNode) : DefNode(name(c), f(value(c)))
       (c:DefInstance) : DefInstance(name(c), f(module(c)))
       (c:Conditionally) : Conditionally(f(pred(c)), conseq(c), alt(c))
       (c:Connect) : Connect(f(loc(c)), f(exp(c)))
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 4a5634d0..25ce27bd 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -49,33 +49,61 @@ defstruct WDefAccessor <: Stmt :
    dir: Direction
 
 ;================ WORKING IR UTILS =========================
+;============== DEBUG STUFF =============================
+public var PRINT-TYPES : True|False = false
+public var PRINT-KINDS : True|False = false
+public var PRINT-WIDTHS : True|False = false
+public var PRINT-CIRCUITS : True|False = false
 ;=== Printers ===
 defmethod print (o:OutputStream, k:Kind) :
    print{o, _} $
    match(k) :
-      (k:RegKind) : "reg:"
-      (k:AccessorKind) : "accessor:"
-      (k:PortKind) : "port:"
-      (k:MemKind) : "mem:"
-      (k:NodeKind) : "n:"
-      (k:ModuleKind) : "module:"
-      (k:InstanceKind) : "inst:"
-      (k:StructuralMemKind) : "smem:"
-
+      (k:RegKind) : "reg"
+      (k:AccessorKind) : "accessor"
+      (k:PortKind) : "port"
+      (k:MemKind) : "mem"
+      (k:NodeKind) : "n"
+      (k:ModuleKind) : "module"
+      (k:InstanceKind) : "inst"
+      (k:StructuralMemKind) : "smem"
+
+defn hasWidth (e:Expression|Stmt|Type|Element|Port) :
+   e typeof UIntType|SIntType|UIntValue|SIntValue
+
+defn hasType (e:Expression|Stmt|Type|Element|Port) :
+   e typeof Ref|Field|Index|DoPrim|ReadPort|WRef|WField
+      |WIndex|DefWire|DefRegister|DefMemory|Register
+      |Memory|Node|Instance|VectorType|Port
+
+defn hasKind (e:Expression|Stmt|Type|Element|Port) :
+   e typeof WRef
+
+defn any-debug? (e:Expression|Stmt|Type|Element|Port) : 
+   (hasType(e) and PRINT-TYPES) or
+   (hasWidth(e) and PRINT-WIDTHS) or
+   (hasKind(e) and PRINT-KINDS)
+
+defmethod print-debug (o:OutputStream, e:Expression|Stmt|Type|Element|Port) :
+   if any-debug?(e) : print(o,"@")
+   if PRINT-KINDS and hasKind(e) : print-all(o,["<k:" kind(e as ?) ">"])
+   if PRINT-TYPES and hasType(e) : print-all(o,["<t:" type(e as ?) ">"])
+   if PRINT-WIDTHS and hasWidth(e): print-all(o,["<w:" width(e as ?) ">"])
+      
 defmethod print (o:OutputStream, e:WRef) :
-   if PRINT-TYPES :
-      print-all(o,[kind(e) name(e) ":" type(e)])
-   else : 
-      print-all(o,[kind(e) name(e)])
+   print(o,name(e))
+   print-debug(o,e as ?)
 
 defmethod print (o:OutputStream, e:WField) :
    print-all(o,[exp(e) "." name(e)])
+   print-debug(o,e as ?)
 
 defmethod print (o:OutputStream, e:WIndex) :
    print-all(o,[exp(e) "." value(e)])
+   print-debug(o,e as ?)
 
 defmethod print (o:OutputStream, s:WDefAccessor) :
-  print-all(o,[dir(s) " accessor " name(s) " = " source(s) "[" index(s) "]"])
+   print-all(o,[dir(s) " accessor " name(s) " = " source(s) "[" index(s) "]"])
+   print-debug(o,s)
 
 defmethod map (f: Expression -> Expression, e: WField) :
    WField(f(exp(e)), name(e), type(e), dir(e))
@@ -1896,10 +1924,14 @@ defn inline-instances (c:Circuit) :
 ;============= DRIVER ======================================
 public defn run-passes (c: Circuit, p: List<Char>) :
    var c*:Circuit = c
+   println("Compiling!")
+   if PRINT-CIRCUITS : println("Original Circuit")
+   if PRINT-CIRCUITS : print(c)
    defn do-stage (name:String, f: Circuit -> Circuit) :
-      println(name)
+      if PRINT-CIRCUITS : println(name)
       c* = f(c*)
-      println(c*)
+      if PRINT-CIRCUITS : print(c*)
+      if PRINT-CIRCUITS : println-all(["Finished " name "\n"])
 
   ; Early passes:
   ;  If modules have a reset defined, must be an INPUT and UInt(1)
@@ -1919,7 +1951,7 @@ public defn run-passes (c: Circuit, p: List<Char>) :
    if contains(p,'n') : do-stage("Pad Widths", pad-widths)
    if contains(p,'o') : do-stage("Inline Instances", inline-instances)
 
-   println("\n\n\n\n")
+   println("Done!")
 
 
  ;;  println("Shim for Jonathan's Passes")