Merge branch 'master' of github.com:ucb-bar/firrtl

6 files changed, 36 insertions, 5 deletions

diff --git a/src/main/resources/logback.xml b/src/main/resources/logback.xml
index 78360578..d2f8beae 100644
--- a/src/main/resources/logback.xml
+++ b/src/main/resources/logback.xml
@@ -30,7 +30,7 @@ MODIFICATIONS.
             <pattern>[%-4level] %msg%n</pattern>
         </encoder>
     </appender>
-    <root level="debug">
+    <root level="warn">
         <appender-ref ref="STDOUT" />
     </root>
 </configuration>
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 0bb7510f..782d43cb 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -38,9 +38,16 @@ trait Compiler extends LazyLogging {
 }
 
 object FIRRTLCompiler extends Compiler {
+  val passes = Seq(
+    CInferTypes,
+    CInferMDir,
+    RemoveCHIRRTL,
+    ToWorkingIR,
+    CheckHighForm
+  )
   def run(c: Circuit, w: Writer) = {
-    FIRRTLEmitter.run(c, w)
-    w.close
+    val highForm = PassUtils.executePasses(c, passes)
+    FIRRTLEmitter.run(highForm, w)
   }
 }
 
@@ -84,7 +91,6 @@ object VerilogCompiler extends Compiler {
   {
     val loweredIR = PassUtils.executePasses(c, passes)
     VerilogEmitter.run(loweredIR, w)
-    w.close
   }
 
 }
diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index c2dc0b59..1e0d9cf1 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -48,6 +48,7 @@ object Driver extends LazyLogging {
     val parsedInput = Parser.parse(input, Source.fromFile(input).getLines)
     val writerOutput = new PrintWriter(new File(output))
     compiler.run(parsedInput, writerOutput)
+    writerOutput.close
   }
 
   def main(args: Array[String])
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 251ae7b2..5fad46bc 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -558,7 +558,7 @@ object Utils {
        case s:DefNode => tpe(s.value)
        case s:DefMemory => {
           val depth = s.depth
-          val addr = Field("addr",DEFAULT,UIntType(IntWidth(ceil_log2(depth))))
+          val addr = Field("addr",DEFAULT,UIntType(IntWidth(scala.math.max(ceil_log2(depth), 1))))
           val en = Field("en",DEFAULT,BoolType())
           val clk = Field("clk",DEFAULT,ClockType())
           val def_data = Field("data",DEFAULT,s.data_type)
diff --git a/src/test/resources/regress b/src/test/resources/regress
new file mode 120000
index 00000000..3691434b
--- /dev/null
+++ b/src/test/resources/regress
@@ -0,0 +1 @@
+../../../regress
\ No newline at end of file
diff --git a/src/test/scala/firrtlTests/Regress.scala b/src/test/scala/firrtlTests/Regress.scala
new file mode 100644
index 00000000..49c95590
--- /dev/null
+++ b/src/test/scala/firrtlTests/Regress.scala
@@ -0,0 +1,23 @@
+
+package firrtlTests
+
+import org.scalatest._
+
+import firrtl._
+import java.io._
+import scala.io.Source
+
+class RocketRegressionSpec extends FlatSpec with Matchers {
+
+  // This test is temporary until we move to simulation-based testing
+  "CHIRRTL Rocket" should "match expected Verilog" in {
+    val firrtlSource = Source.fromURL(getClass.getResource("/regress/rocket.fir"))
+    val highCircuit = firrtl.Parser.parse("rocket.fir", firrtlSource.getLines)
+    val verilogSW = new StringWriter()
+    VerilogCompiler.run(highCircuit, verilogSW)
+
+    val goldenVerilog = Source.fromURL(getClass.getResource("/regress/rocket-golden.v"))
+    
+    verilogSW.toString shouldEqual goldenVerilog.mkString 
+  }
+}