From b487ab24c0e298e7781f74811b8bfcd24384d1b5 Mon Sep 17 00:00:00 2001 From: Jack Date: Mon, 22 Feb 2016 22:59:45 -0800 Subject: Temporary Fix: get_type on depth=1 memories causing IntWidth(0) types --- src/main/scala/firrtl/Utils.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index 251ae7b2..5fad46bc 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -558,7 +558,7 @@ object Utils { case s:DefNode => tpe(s.value) case s:DefMemory => { val depth = s.depth - val addr = Field("addr",DEFAULT,UIntType(IntWidth(ceil_log2(depth)))) + val addr = Field("addr",DEFAULT,UIntType(IntWidth(scala.math.max(ceil_log2(depth), 1)))) val en = Field("en",DEFAULT,BoolType()) val clk = Field("clk",DEFAULT,ClockType()) val def_data = Field("data",DEFAULT,s.data_type) -- cgit v1.2.3 From 087463be7c0591e6e9983d4b8344057cc49db3eb Mon Sep 17 00:00:00 2001 From: Jack Date: Mon, 22 Feb 2016 23:19:31 -0800 Subject: Change default log-level to warn, users should change manually if so desired --- src/main/resources/logback.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/resources/logback.xml b/src/main/resources/logback.xml index 78360578..d2f8beae 100644 --- a/src/main/resources/logback.xml +++ b/src/main/resources/logback.xml @@ -30,7 +30,7 @@ MODIFICATIONS. [%-4level] %msg%n - + -- cgit v1.2.3 From b49add5a991b0f8f6fc25ffdcb4876f4ae19b794 Mon Sep 17 00:00:00 2001 From: Jack Date: Tue, 23 Feb 2016 00:10:40 -0800 Subject: Stop closing writers in compiler, close in Driver instead (allows others to use StringWriters without the Compiler closing it) --- src/main/scala/firrtl/Compiler.scala | 2 -- src/main/scala/firrtl/Driver.scala | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index 0bb7510f..34776cf3 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -40,7 +40,6 @@ trait Compiler extends LazyLogging { object FIRRTLCompiler extends Compiler { def run(c: Circuit, w: Writer) = { FIRRTLEmitter.run(c, w) - w.close } } @@ -84,7 +83,6 @@ object VerilogCompiler extends Compiler { { val loweredIR = PassUtils.executePasses(c, passes) VerilogEmitter.run(loweredIR, w) - w.close } } diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala index c2dc0b59..1e0d9cf1 100644 --- a/src/main/scala/firrtl/Driver.scala +++ b/src/main/scala/firrtl/Driver.scala @@ -48,6 +48,7 @@ object Driver extends LazyLogging { val parsedInput = Parser.parse(input, Source.fromFile(input).getLines) val writerOutput = new PrintWriter(new File(output)) compiler.run(parsedInput, writerOutput) + writerOutput.close } def main(args: Array[String]) -- cgit v1.2.3 From 6ec6edea9a60f8aab80ee287547160ffaf73aaf7 Mon Sep 17 00:00:00 2001 From: Jack Date: Tue, 23 Feb 2016 00:24:33 -0800 Subject: Change FIRRTL Compiler to remove CHIRRTL and Check High FIRRTL Form --- src/main/scala/firrtl/Compiler.scala | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index 34776cf3..782d43cb 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -38,8 +38,16 @@ trait Compiler extends LazyLogging { } object FIRRTLCompiler extends Compiler { + val passes = Seq( + CInferTypes, + CInferMDir, + RemoveCHIRRTL, + ToWorkingIR, + CheckHighForm + ) def run(c: Circuit, w: Writer) = { - FIRRTLEmitter.run(c, w) + val highForm = PassUtils.executePasses(c, passes) + FIRRTLEmitter.run(highForm, w) } } -- cgit v1.2.3 From c48c691e94afe4919c20fa588a9897316c572447 Mon Sep 17 00:00:00 2001 From: Jack Date: Tue, 23 Feb 2016 00:57:09 -0800 Subject: Add rocket regression, just runs rocket.fir through Verilog compiler and compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip --- src/test/resources/regress | 1 + src/test/scala/firrtlTests/Regress.scala | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 120000 src/test/resources/regress create mode 100644 src/test/scala/firrtlTests/Regress.scala (limited to 'src') diff --git a/src/test/resources/regress b/src/test/resources/regress new file mode 120000 index 00000000..3691434b --- /dev/null +++ b/src/test/resources/regress @@ -0,0 +1 @@ +../../../regress \ No newline at end of file diff --git a/src/test/scala/firrtlTests/Regress.scala b/src/test/scala/firrtlTests/Regress.scala new file mode 100644 index 00000000..49c95590 --- /dev/null +++ b/src/test/scala/firrtlTests/Regress.scala @@ -0,0 +1,23 @@ + +package firrtlTests + +import org.scalatest._ + +import firrtl._ +import java.io._ +import scala.io.Source + +class RocketRegressionSpec extends FlatSpec with Matchers { + + // This test is temporary until we move to simulation-based testing + "CHIRRTL Rocket" should "match expected Verilog" in { + val firrtlSource = Source.fromURL(getClass.getResource("/regress/rocket.fir")) + val highCircuit = firrtl.Parser.parse("rocket.fir", firrtlSource.getLines) + val verilogSW = new StringWriter() + VerilogCompiler.run(highCircuit, verilogSW) + + val goldenVerilog = Source.fromURL(getClass.getResource("/regress/rocket-golden.v")) + + verilogSW.toString shouldEqual goldenVerilog.mkString + } +} -- cgit v1.2.3