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authorJack Koenig2018-01-30 18:11:00 -0800
committerGitHub2018-01-30 18:11:00 -0800
commit57025111d3bc872da726e31e3e9a1e4895593266 (patch)
tree70de3e10760efef858ca78a4e181e28d30984abe /src
parent47d2bb1f447644ee0bcc44701bc84018cc5795b9 (diff)
parentc9d3e257bff74235a75ff5530051e419b9ce8005 (diff)
Merge pull request #735 from freechipsproject/fix-const-prop
Fix Bugs in Constant Propagation
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/transforms/ConstantPropagation.scala11
-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala25
2 files changed, 28 insertions, 8 deletions
diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
index ca48cbb5..d08a7e6b 100644
--- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala
+++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
@@ -367,7 +367,7 @@ class ConstantPropagation extends Transform {
// Const prop registers that are fed only a constant or a mux between and constant and the
// register itself
// This requires that reset has been made explicit
- case Connect(_, lref @ WRef(lname, ltpe, RegKind, _), expr) => expr match {
+ case Connect(_, lref @ WRef(lname, ltpe, RegKind, _), expr) if !dontTouches.contains(lname) => expr match {
case lit: Literal =>
nodeMap(lname) = constPropExpression(pad(lit, ltpe))
case Mux(_, tval: WRef, fval: Literal, _) if weq(lref, tval) =>
@@ -407,8 +407,13 @@ class ConstantPropagation extends Transform {
mod.module -> children.map(i => i.name -> i.module).toMap
})
- // Module name to number of instances
- val instCount: Map[String, Int] = iGraph.getVertices.groupBy(_.module).mapValues(_.size)
+ // This is a *relative* instance count, ie. how many there are when you visit each Module once
+ // (even if it is instantiated multiple times)
+ val instCount: Map[String, Int] = iGraph.getEdgeMap.foldLeft(Map(c.main -> 1)) {
+ case (cs, (_, values)) => values.foldLeft(cs) {
+ case (counts, value) => counts.updated(value.module, counts.getOrElse(value.module, 0) + 1)
+ }
+ }
// DiGraph using Module names as nodes, destination of edge is a parent Module
val parentGraph: DiGraph[String] = iGraph.reverse.transformNodes(_.module)
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 06e24b97..e143f853 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -67,9 +67,9 @@ s"""circuit Top :
out <= in
module Child :
output out : UInt<1>
- inst b of Bottom
- b.in <= UInt(1)
- out <= b.out
+ inst b0 of Bottom
+ b0.in <= UInt(1)
+ out <= b0.out
module Top :
input x : UInt<1>
output z : UInt<1>
@@ -91,8 +91,8 @@ s"""circuit Top :
out <= UInt(1)
module Child :
output out : UInt<1>
- inst b of Bottom
- b.in <= UInt(1)
+ inst b0 of Bottom
+ b0.in <= UInt(1)
out <= UInt(1)
module Top :
input x : UInt<1>
@@ -712,6 +712,21 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
execute(input, check, Seq(dontTouch("Top.z")))
}
+ "ConstProp" should "NOT optimize across dontTouch on registers" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | input clk : Clock
+ | input reset : UInt<1>
+ | output y : UInt<1>
+ | reg z : UInt<1>, clk
+ | y <= z
+ | z <= mux(reset, UInt<1>("h0"), z)""".stripMargin
+ val check = input
+ execute(input, check, Seq(dontTouch("Top.z")))
+ }
+
+
it should "NOT optimize across dontTouch on wires" in {
val input =
"""circuit Top :