Merge pull request #291 from ucb-bar/case_object_WVoid_WInvalid

Case object for WVoid WInvalid

9 files changed, 21 insertions, 23 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 85955088..26b1f3d9 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -53,7 +53,6 @@ object FIRRTLEmitter extends Emitter {
   def run(c: Circuit, w: Writer) = w.write(c.serialize)
 }
 
-case class VIndent()
 case class VRandom(width: BigInt) extends Expression {
   def tpe = UIntType(IntWidth(width))
   def nWords = (width + 31) / 32
@@ -127,7 +126,6 @@ class VerilogEmitter extends Emitter {
       case (i: Int) => w write i.toString
       case (i: Long) => w write i.toString
       case (i: BigInt) => w write i.toString
-      case (t: VIndent) => w write "   "
       case (s: Seq[Any]) =>
         s foreach (emit(_, top + 1))
         if (top == 0) w write "\n"
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index be4700e3..bc1ca704 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -337,7 +337,7 @@ object Utils extends LazyLogging {
     case e: SIntLiteral => MALE
     case e: Mux => MALE
     case e: ValidIf => MALE
-    case e: WInvalid => MALE
+    case WInvalid => MALE
     case e => println(e); error("Shouldn't be here")
   }
   def get_gender(s: Statement): Gender = s match {
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index 9c63360c..06b5be48 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -73,14 +73,14 @@ case class WSubAccess(exp: Expression, index: Expression, tpe: Type, gender: Gen
   def mapType(f: Type => Type): Expression = this.copy(tpe = f(tpe))
   def mapWidth(f: Width => Width): Expression = this
 }
-case class WVoid() extends Expression {
+case object WVoid extends Expression {
   def tpe = UnknownType
   def serialize: String = "VOID"
   def mapExpr(f: Expression => Expression): Expression = this
   def mapType(f: Type => Type): Expression = this
   def mapWidth(f: Width => Width): Expression = this
 }
-case class WInvalid() extends Expression {
+case object WInvalid extends Expression {
   def tpe = UnknownType
   def serialize: String = "INVALID"
   def mapExpr(f: Expression => Expression): Expression = this
@@ -126,8 +126,8 @@ class WrappedExpression (val e1: Expression) {
        case (e1: WSubField, e2: WSubField) => (e1.name equals e2.name) && weq(e1.exp,e2.exp)
        case (e1: WSubIndex, e2: WSubIndex) => (e1.value == e2.value) && weq(e1.exp,e2.exp)
        case (e1: WSubAccess, e2: WSubAccess) => weq(e1.index,e2.index) && weq(e1.exp,e2.exp)
-       case (e1: WVoid, e2: WVoid) => true
-       case (e1: WInvalid, e2: WInvalid) => true
+       case (WVoid, WVoid) => true
+       case (WInvalid, WInvalid) => true
        case (e1: DoPrim, e2: DoPrim) => e1.op == e2.op &&
           ((e1.consts zip e2.consts) forall {case (x, y) => x == y}) &&
           ((e1.args zip e2.args) forall {case (x, y) => weq(x, y)})
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index f90ee277..7d7f2f32 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -69,7 +69,7 @@ object CheckInitialization extends Pass {
         var void = false
         val voidDeps = collection.mutable.ArrayBuffer[Expression]()
         def hasVoid(e: Expression): Expression = e match {
-          case e: WVoid =>
+          case WVoid =>
             void = true
             e
           case (_: WRef | _: WSubField) =>
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 6bd4bffd..4cc0bdb9 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -63,7 +63,7 @@ object ExpandWhens extends Pass {
   }
   private def expandNetlist(netlist: Netlist) =
     netlist map {
-      case (k, WInvalid()) => IsInvalid(NoInfo, k.e1)
+      case (k, WInvalid) => IsInvalid(NoInfo, k.e1)
       case (k, v) => Connect(NoInfo, k.e1, v)
     }
   // Searches nested scopes of defaults for lvalue
@@ -80,9 +80,9 @@ object ExpandWhens extends Pass {
   }
 
   private def AND(e1: Expression, e2: Expression) =
-    DoPrim(And, Seq(e1, e2), Nil, UIntType(IntWidth(1)))
+    DoPrim(And, Seq(e1, e2), Nil, BoolType)
   private def NOT(e: Expression) =
-    DoPrim(Eq, Seq(e, zero), Nil, UIntType(IntWidth(1)))
+    DoPrim(Eq, Seq(e, zero), Nil, BoolType)
 
   // ------------ Pass -------------------
   def run(c: Circuit): Circuit = {
@@ -97,7 +97,7 @@ object ExpandWhens extends Pass {
                       p: Expression)
                       (s: Statement): Statement = s match {
         case w: DefWire =>
-          netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid()))
+          netlist ++= (getFemaleRefs(w.name, w.tpe, BIGENDER) map (ref => we(ref) -> WVoid))
           w
         case r: DefRegister =>
           netlist ++= (getFemaleRefs(r.name, r.tpe, BIGENDER) map (ref => we(ref) -> ref))
@@ -106,7 +106,7 @@ object ExpandWhens extends Pass {
           netlist(c.loc) = c.expr
           EmptyStmt
         case c: IsInvalid =>
-          netlist(c.expr) = WInvalid()
+          netlist(c.expr) = WInvalid
           EmptyStmt
         case s: Conditionally =>
           val conseqNetlist = new Netlist
@@ -127,9 +127,9 @@ object ExpandWhens extends Pass {
                 val trueValue = conseqNetlist getOrElse (lvalue, defaultValue)
                 val falseValue = altNetlist getOrElse (lvalue, defaultValue)
                 (trueValue, falseValue) match {
-                  case (WInvalid(), WInvalid()) => WInvalid()
-                  case (WInvalid(), fv) => ValidIf(NOT(s.pred), fv, fv.tpe)
-                  case (tv, WInvalid()) => ValidIf(s.pred, tv, tv.tpe)
+                  case (WInvalid, WInvalid) => WInvalid
+                  case (WInvalid, fv) => ValidIf(NOT(s.pred), fv, fv.tpe)
+                  case (tv, WInvalid) => ValidIf(s.pred, tv, tv.tpe)
                   case (tv, fv) => Mux(s.pred, tv, fv, mux_type_and_widths(tv, fv))
                 }
               case None =>
@@ -165,7 +165,7 @@ object ExpandWhens extends Pass {
       val netlist = new Netlist
       // Add ports to netlist
       netlist ++= (m.ports flatMap { case Port(_, name, dir, tpe) =>
-        getFemaleRefs(name, tpe, to_gender(dir)) map (ref => we(ref) -> WVoid())
+        getFemaleRefs(name, tpe, to_gender(dir)) map (ref => we(ref) -> WVoid)
       })
       (netlist, simlist, expandWhens(netlist, Seq(netlist), one)(m.body))
     }
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 21884661..505ad0da 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -193,7 +193,7 @@ object MemPortUtils {
 
   def rwPortToFlattenBundle(mem: DefMemory) = BundleType(
     defaultPortSeq(mem) ++ Seq(
-      Field("wmode", Default, UIntType(IntWidth(1))),
+      Field("wmode", Default, BoolType),
       Field("wdata", Default, flattenType(mem.dataType)),
       Field("rdata", Flip, flattenType(mem.dataType))
     ) ++ (if (!containsInfo(mem.info, "maskGran")) Nil
@@ -220,7 +220,7 @@ object MemPortUtils {
       Field("mask", Default, createMask(mem.dataType))))
     val rwType = BundleType(defaultPortSeq(mem) ++ Seq(
       Field("rdata", Flip, mem.dataType),
-      Field("wmode", Default, UIntType(IntWidth(1))),
+      Field("wmode", Default, BoolType),
       Field("wdata", Default, mem.dataType),
       Field("wmask", Default, createMask(mem.dataType))))
     BundleType(
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 9057c60d..7f53fac8 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -200,9 +200,9 @@ object Legalize extends Pass {
     lazy val msb = width - 1
     if (amount >= width) {
       e.tpe match {
-        case UIntType(_) => UIntLiteral(0, IntWidth(1))
+        case UIntType(_) => zero
         case SIntType(_) =>
-          val bits = DoPrim(Bits, e.args, Seq(msb, msb), UIntType(IntWidth(1)))
+          val bits = DoPrim(Bits, e.args, Seq(msb, msb), BoolType)
           DoPrim(AsSInt, Seq(bits), Seq.empty, SIntType(IntWidth(1)))
         case t => error(s"Unsupported type ${t} for Primop Shift Right")
       }
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index 08f08eac..933c3543 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -15,7 +15,7 @@ object RemoveAccesses extends Pass {
   def name = "Remove Accesses"
 
   private def AND(e1: Expression, e2: Expression) =
-    DoPrim(And, Seq(e1, e2), Nil, UIntType(IntWidth(1)))
+    DoPrim(And, Seq(e1, e2), Nil, BoolType)
 
   private def EQV(e1: Expression, e2: Expression): Expression =
     DoPrim(Eq, Seq(e1, e2), Nil, e1.tpe)
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index ca860ab6..b71c0dc3 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -174,7 +174,7 @@ object RemoveCHIRRTL extends Pass {
         case Some(p) => g match {
           case FEMALE =>
             has_write_mport = true
-            if (p.rdwrite) has_readwrite_mport = Some(SubField(p.exp, "wmode", UIntType(IntWidth(1))))
+            if (p.rdwrite) has_readwrite_mport = Some(SubField(p.exp, "wmode", BoolType))
             SubField(p.exp, p.female, tpe)
           case MALE =>
             SubField(p.exp, p.male, tpe)