Fixed minor bugs, but looks like there is a stanza bug. This blows. And sucks.

3 files changed, 12 insertions, 9 deletions

diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index a9ddf817..8c650f36 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -272,8 +272,10 @@ rd.defsyntax firrtl :
       (ReadPort (@do ?mem:#exp ?index:#exp ?enable:#exp)) :
          ReadPort(mem, index, UnknownType(), enable)
       (?op:#symbol (@do ?es:#exp ... ?ints:#int ...)) :
+         println("Op-symbol is:~" % [op])
          match(get?(operators, ut(op), false)) :
             (op:PrimOp) :
+               println("Op is:~ ~" % [op,op == ADD-OP])
                DoPrim(op, es, map(ut, ints), UnknownType())
             (f:False) :
                throw-error $ string-join $ [
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 1149af3f..aebaf0f9 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -151,29 +151,30 @@ defmethod print (o:OutputStream, c:Stmt) :
          println(o, "in :")
          print(io, body(c))
       (c:DefWire) :
-         print-all(["wire " name(c) " : " type(c)])
+         print-all(o,["wire " name(c) " : " type(c)])
       (c:DefRegister) : 
-         print-all(["reg " name(c) " : " type(c)])
+         print-all(o,["reg " name(c) " : " type(c)])
       (c:DefMemory) :
-         print-all(["mem " name(c) " : " type(c)])
+         print-all(o,["mem " name(c) " : " type(c)])
       (c:DefInstance) :
-         print-all(["inst " name(c) " of " module(c)])
+         print-all(o,["inst " name(c) " of " module(c)])
       (c:DefNode) :
-         print-all(["node " name(c) " = " value(c)])      
+         print-all(o,["node " name(c) " = " value(c)])      
       (c:DefAccessor) :
-         print-all(["accessor " name(c) " = " source(c) "[" index(c) "]"])      
+         print-all(o,["accessor " name(c) " = " source(c) "[" index(c) "]"])      
       (c:Conditionally) :
          println-all(o, ["when " pred(c) " :"])
          print(io,conseq(c))
          if alt(c) not-typeof EmptyStmt :
-            println(o, "\nelse :")
+            print(o, "\nelse :")
+            print(io, "\n")
             print(io,alt(c))
       (c:Begin) :
          do(print{o,_}, join(body(c), "\n"))
       (c:Connect) :
          print-all(o, [loc(c) " := " exp(c)])
       (c:EmptyStmt) :
-         print(o, "skip")
+         print(o, "ip")
    print-debug(o,c)
 
 defmethod print (o:OutputStream, e:Element) :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index ad165353..324630f0 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -869,7 +869,7 @@ defn lower-module (m:Module,table:HashTable<Symbol,List<KeyValue<Expression,Flip
          (s:DefWire) : table[name(s)] = get-entries(name(s),type(s))
          (s:DefRegister) : 
             table[name(s)] = get-entries(name(s),type(s))
-            table[to-symbol("~.init" % to-string(name(s)))] = get-entries(to-symbol("~#init" % to-string(name(s))),type(s)) ; TODO, we are keeping WRegInits around
+            table[to-symbol("~.init" % [to-string(name(s))])] = get-entries(to-symbol("~#init" % [to-string(name(s))]),type(s)) ; TODO, we are keeping WRegInits around
          (s:DefInstance) : 
             val r = WRef(name(s),type(module(s)),InstanceKind(),FEMALE)
             val ports = table[name(module(s) as WRef)]