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authorazidar2015-03-24 10:24:11 -0700
committerazidar2015-03-24 10:24:11 -0700
commit8d43a884af141651eefdb049b52ab4fd3356763b (patch)
tree6e7f4bddc38411995fd3dbd23556f1771e0fd81e /src
parent3e6d0e2b290aeb49aa9085b75b8a6c57fe1af28c (diff)
With new stanza
Diffstat (limited to 'src')
-rw-r--r--src/lib/stanza.zipbin0 -> 3642327 bytes
-rw-r--r--src/lib/stanzam.zipbin2167258 -> 0 bytes
-rw-r--r--src/main/stanza/firrtl-main.stanza2
-rw-r--r--src/main/stanza/firrtl-test-main.stanza5
-rw-r--r--src/main/stanza/ir-parser.stanza6
-rw-r--r--src/main/stanza/ir-utils.stanza48
-rw-r--r--src/main/stanza/passes.stanza33
7 files changed, 50 insertions, 44 deletions
diff --git a/src/lib/stanza.zip b/src/lib/stanza.zip
new file mode 100644
index 00000000..85d8c9e2
--- /dev/null
+++ b/src/lib/stanza.zip
Binary files differ
diff --git a/src/lib/stanzam.zip b/src/lib/stanzam.zip
deleted file mode 100644
index cc396d61..00000000
--- a/src/lib/stanzam.zip
+++ /dev/null
Binary files differ
diff --git a/src/main/stanza/firrtl-main.stanza b/src/main/stanza/firrtl-main.stanza
index 4c7ecaab..38b24815 100644
--- a/src/main/stanza/firrtl-main.stanza
+++ b/src/main/stanza/firrtl-main.stanza
@@ -1,7 +1,7 @@
include<"core/stringeater.stanza">
include<"compiler/lexer.stanza">
include<"compiler/parser.stanza">
-include<"compiler/rdparser2.stanza">
+include<"compiler/rdparser.stanza">
include<"compiler/macro-utils.stanza">
include("firrtl-ir.stanza")
include("ir-utils.stanza")
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 80c5e257..e9cff931 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -1,7 +1,7 @@
include<"core/stringeater.stanza">
include<"compiler/lexer.stanza">
include<"compiler/parser.stanza">
-include<"compiler/rdparser2.stanza">
+include<"compiler/rdparser.stanza">
include<"compiler/macro-utils.stanza">
include("firrtl-ir.stanza")
include("ir-utils.stanza")
@@ -26,8 +26,7 @@ defn set-printvars! (p:List<Char>) :
if contains(p,'c') : PRINT-CIRCUITS = true
defn main () :
- val arg = commandline-arguments()
- val args = split(arg,' ')
+ val args = commandline-arguments()
val lexed = lex-file(args[1])
val c = parse-firrtl(lexed)
if length(args) >= 4 :
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 46b62162..a9ddf817 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -37,7 +37,7 @@ defn split-string (s:String, split:String) -> List<String> :
loop(s)
;======= Unwrap Prefix Forms ============
-defn unwrap-prefix-form (form) :
+defn unwrap-prefix-form (form) -> ? :
match(form) :
(form:Token) :
val fs = unwrap-prefix-form(item(form))
@@ -53,12 +53,12 @@ defn unwrap-prefix-form (form) :
list(form)
;======= Split Dots ============
-defn split-dots (forms:List) :
+defn split-dots (forms:List) -> ? :
defn to-form (x:String) :
val num? = for c in x all? :
c >= '0' and c <= '9'
to-int(x) when num? else to-symbol(x)
- defn split (form) :
+ defn split (form) -> List:
match(ut(form)) :
(f:Symbol) :
val fstr = to-string(f)
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index b023b995..1149af3f 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -142,14 +142,14 @@ defmethod print (o:OutputStream, e:Expression) :
print-debug(o,e)
defmethod print (o:OutputStream, c:Stmt) :
+ val io = IndentedStream(o, 3)
match(c) :
(c:LetRec) :
println(o, "let : ")
- indented{o, _} $ fn () :
- for entry in entries(c) do :
- println-all([key(entry) " = " value(entry)])
+ for entry in entries(c) do :
+ println-all(io,[key(entry) " = " value(entry)])
println(o, "in :")
- indented(o, print{o, body(c)})
+ print(io, body(c))
(c:DefWire) :
print-all(["wire " name(c) " : " type(c)])
(c:DefRegister) :
@@ -164,12 +164,12 @@ defmethod print (o:OutputStream, c:Stmt) :
print-all(["accessor " name(c) " = " source(c) "[" index(c) "]"])
(c:Conditionally) :
println-all(o, ["when " pred(c) " :"])
- indented(o, print{conseq(c)})
+ print(io,conseq(c))
if alt(c) not-typeof EmptyStmt :
println(o, "\nelse :")
- indented(o, print{alt(c)})
+ print(io,alt(c))
(c:Begin) :
- do(print, join(body(c), "\n"))
+ do(print{o,_}, join(body(c), "\n"))
(c:Connect) :
print-all(o, [loc(c) " := " exp(c)])
(c:EmptyStmt) :
@@ -222,36 +222,16 @@ defmethod print (o:OutputStream, p:Port) :
defmethod print (o:OutputStream, m:Module) :
println-all(o, ["module " name(m) " :"])
- indented{o, _} $ fn () :
- do(println, ports(m))
- print(body(m))
+ val io = IndentedStream(o, 3)
+ for p in ports(m) do :
+ println(io,p)
+ print(io,body(m))
defmethod print (o:OutputStream, c:Circuit) :
println-all(o, ["circuit " main(c) " :"])
- indented(o, do{println, modules(c)})
-
-;================== INDENTATION ============================
-defn IndentedStream (o:OutputStream, n:Int) :
- var indent? = true
- defn put (c:Char) :
- if indent? :
- do(print{o, " "}, 0 to n)
- indent? = false
- print(o, c)
- if c == '\n' :
- indent? = true
-
- new OutputStream :
- defmethod print (this, s:String) : do(put, s)
- defmethod print (this, c:Char) : put(c)
-
-defn indented (o:OutputStream, f: () -> ?) :
- val prev-stream = CURRENT-OUTPUT-STREAM
- dynamic-wind(
- fn () : CURRENT-OUTPUT-STREAM = IndentedStream(o, 3)
- f
- fn (f) : CURRENT-OUTPUT-STREAM = prev-stream)
-
+ val io = IndentedStream(o, 3)
+ for m in modules(c) do :
+ println(io, m)
;=================== MAPPERS ===============================
public defn map<?T> (f: Type -> Type, t:?T&Type) -> T :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 4ee39fb3..ad165353 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -231,7 +231,7 @@ defn to-working-ir (c:Circuit) :
match(map(to-exp,e)) :
(e:Ref) : WRef(name(e), type(e), NodeKind(), UNKNOWN-GENDER)
(e:Subfield) :
- if name(e) == `init : WRegInit(exp(e), to-symbol(to-string(name(exp(e) as WRef)) + ".init"), type(e), UNKNOWN-GENDER)
+ if name(e) == `init : WRegInit(exp(e), to-symbol("~.init" % [name(exp(e) as WRef)]), type(e), UNKNOWN-GENDER)
else : WSubfield(exp(e), name(e), type(e), UNKNOWN-GENDER)
(e:Index) : WIndex(exp(e), value(e), type(e), UNKNOWN-GENDER)
(e) : e
@@ -869,7 +869,7 @@ defn lower-module (m:Module,table:HashTable<Symbol,List<KeyValue<Expression,Flip
(s:DefWire) : table[name(s)] = get-entries(name(s),type(s))
(s:DefRegister) :
table[name(s)] = get-entries(name(s),type(s))
- table[to-symbol(to-string(name(s)) + ".init")] = get-entries(to-symbol(to-string(name(s))+ "#init"),type(s))
+ table[to-symbol("~.init" % to-string(name(s)))] = get-entries(to-symbol("~#init" % to-string(name(s))),type(s)) ; TODO, we are keeping WRegInits around
(s:DefInstance) :
val r = WRef(name(s),type(module(s)),InstanceKind(),FEMALE)
val ports = table[name(module(s) as WRef)]
@@ -984,7 +984,34 @@ defmethod map (f: SymbolicValue -> SymbolicValue, sv:SymbolicValue) -> SymbolicV
defn new-vec () -> Vector<KeyValue<Symbol,[Stmt SymbolicValue]>> :
Vector<KeyValue<Symbol,[Stmt SymbolicValue]>>()
-;defn expand-whens (table:HashTable,KeyValue<Symbol,[Kind SymbolicValue]>>) -> Stmt :
+;defn expand-whens (table:List<KeyValue<Symbol,[Stmt SymbolicValue]>>) -> HashMap<Symbol,SymbolicValue> :
+; val enables = HashMap<Symbol,SymbolicValue>(symbol-hash)
+; for x in table do :
+; val [s sv] = value(x)
+; val sym = key(x)
+; val sv* =
+; match(s) :
+; (s:WDefAccessor) :
+; switch {_ == gender(s)} :
+; FEMALE :
+; defn get-enable (sv:SymbolicValue) -> SymbolicValue :
+; match(map(get-enable,sv)) :
+; (sv: SVExp) : SVExp(UIntValue(1,1))
+; (sv: SVNul) : SVExp(UIntValue(0,1))
+; (sv) : sv
+; get-enable(sv)
+; MALE :
+; for y in table do :
+; val [ys ysv] = value(y)
+; if contains?(key(x),ysv) :
+;
+; defn get-enable (sym:Symbol,sv:SymbolicValue) -> SymbolicValue :
+; defn active (e:Expression) ->
+; match(map(get-enable,sv)) :
+; (sv: SVExp) : exp
+; (sv: SVNul) : SVExp(UIntValue(0,1))
+; (sv) : sv
+
defn optimize-table (table:List<KeyValue<Symbol,[Stmt SymbolicValue]>>) -> List<KeyValue<Symbol,[Stmt SymbolicValue]>>:
defn optimize (sv:SymbolicValue) -> SymbolicValue :