diff options
| author | Schuyler Eldridge | 2018-11-01 16:18:16 -0400 |
|---|---|---|
| committer | GitHub | 2018-11-01 16:18:16 -0400 |
| commit | ece8e1b0bb459fd5aa139390b6cb7d313077d21d (patch) | |
| tree | 5626a130bc1607e6a4c68eec864b7944f3a322e8 /src/test | |
| parent | 297fbda180584cc3456145faecdc40418babeef1 (diff) | |
| parent | 9bc2e6daaf3a3a08aefe485aa924c820689de981 (diff) | |
Merge pull request #928 from freechipsproject/dont-append-to-lists
Adds performance improvements by removing list appends.
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 1 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/WidthSpec.scala | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index 62ed561e..2cf9c001 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -95,6 +95,7 @@ class UnitTests extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, + ResolveGenders, ExpandConnects) val input = """circuit Unit : diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala index 9ca965f6..ab8cb7ac 100644 --- a/src/test/scala/firrtlTests/WidthSpec.scala +++ b/src/test/scala/firrtlTests/WidthSpec.scala @@ -53,6 +53,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, + ResolveGenders, InferWidths, CheckWidths) val input = @@ -75,6 +76,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, + ResolveGenders, InferWidths, CheckWidths) val input = @@ -93,6 +95,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, + ResolveGenders, InferWidths, CheckWidths) val input = @@ -117,6 +120,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, + ResolveGenders, InferWidths) val input = """circuit Unit : @@ -138,6 +142,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, + ResolveGenders, InferWidths) val input = """circuit Unit : |