Fixed the check for bundle equality to allow relative flips to be wrong, but the leaf directions are the same

1 files changed, 33 insertions, 4 deletions

diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 14e8562b..f8af4943 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -30,10 +30,11 @@ package firrtlTests
 import java.io._
 import org.scalatest._
 import org.scalatest.prop._
-import firrtl.{Parser,Circuit}
-import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassExceptions}
+import firrtl.{Parser,Circuit,FIRRTLEmitter}
+import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,ExpandConnects,PassExceptions}
 
 class UnitTests extends FlatSpec with Matchers {
+  def parse (input:String) = Parser.parse("",input.split("\n").toIterator,false)
   "Connecting bundles of different types" should "throw an exception" in {
     val passes = Seq(
       ToWorkingIR,
@@ -48,7 +49,7 @@ class UnitTests extends FlatSpec with Matchers {
         |    output x: {a : UInt<1>, b : UInt<1>}
         |    x <= y""".stripMargin
     intercept[PassExceptions] {
-      passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+      passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
     }
@@ -70,9 +71,37 @@ class UnitTests extends FlatSpec with Matchers {
        |    reg y : { valid : UInt<1>, bits : UInt<3> }, clk with :
        |      reset => (reset, x)""".stripMargin
     intercept[PassExceptions] {
-      passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+      passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
     }
   }
+
+  "Partial connection two bundle types whose relative flips don't match but leaf node directions do" should "connect correctly" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      ExpandConnects)
+    val input =
+     """circuit Unit :
+       |  module Unit :
+       |    wire x : { flip a: { b: UInt<32> } }
+       |    wire y : { a: { flip b: UInt<32> } }
+       |    x <- y""".stripMargin
+    val check =
+     """circuit Unit :
+       |  module Unit :
+       |    wire x : { flip a: { b: UInt<32> } }
+       |    wire y : { a: { flip b: UInt<32> } }
+       |    y.a.b <= x.a.b""".stripMargin
+    val c_result = passes.foldLeft(parse(input)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+    val writer = new StringWriter()
+    FIRRTLEmitter.run(c_result,writer)
+    (parse(writer.toString())) should be (parse(check))
+  }
 }