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authorJack Koenig2017-06-28 11:50:25 -0700
committerGitHub2017-06-28 11:50:25 -0700
commit8eb69dd91e58915f8dad5e42da0a3fe686c628d8 (patch)
treec282e0dfe37de7a49271d9a1da364606fe35cf1a /src/test
parentf8572ba6532359e8a0f1bc34f3eb8241a29129ab (diff)
parentca01018fb144dcd206735973e5aa302dbc552ea8 (diff)
Merge pull request #615 from freechipsproject/remove-reset
Remove reset and fix bug in register update Verilog emission
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/IntegrationSpec.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala
index 6ac45b6d..647aa91b 100644
--- a/src/test/scala/firrtlTests/IntegrationSpec.scala
+++ b/src/test/scala/firrtlTests/IntegrationSpec.scala
@@ -11,6 +11,7 @@ import java.io.File
class GCDExecutionTest extends ExecutionTest("GCDTester", "/integration")
class RightShiftExecutionTest extends ExecutionTest("RightShiftTester", "/integration")
class MemExecutionTest extends ExecutionTest("MemTester", "/integration")
+class PipeExecutionTest extends ExecutionTest("PipeTester", "/integration")
// This is a bit custom some kind of one off
class GCDSplitEmissionExecutionTest extends FirrtlFlatSpec {