From 6f55a30b201716b6a0e72b65f6e5777b6b5d4b81 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 27 Jun 2017 17:25:57 -0700
Subject: Emitting reg update mux tree, only walk netlist for wires and nodes

Fixes bug where the Verilog emitter could pull the next value for a
register that feeds a second register, removing the first register from
the second register's update.
---
 src/test/scala/firrtlTests/IntegrationSpec.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala
index 6ac45b6d..647aa91b 100644
--- a/src/test/scala/firrtlTests/IntegrationSpec.scala
+++ b/src/test/scala/firrtlTests/IntegrationSpec.scala
@@ -11,6 +11,7 @@ import java.io.File
 class GCDExecutionTest extends ExecutionTest("GCDTester", "/integration")
 class RightShiftExecutionTest extends ExecutionTest("RightShiftTester", "/integration")
 class MemExecutionTest extends ExecutionTest("MemTester", "/integration")
+class PipeExecutionTest extends ExecutionTest("PipeTester", "/integration")
 
 // This is a bit custom some kind of one off
 class GCDSplitEmissionExecutionTest extends FirrtlFlatSpec {
-- 
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