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authorAlbert Magyar2020-03-25 12:24:58 -0700
committerAlbert Magyar2020-03-26 11:14:28 -0700
commit4b3b5442bfe34502862eb070854aeef1e0cfc9c4 (patch)
tree49e09570ba220679ca51249ea9cb83f101ef66fa /src/test
parent9995f081291d974a6b5ad319e67a9d19cdc4a56d (diff)
Support octal and binary literal formats as described in the spec
* Fixes #1464
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/ParserSpec.scala32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala
index 3958bfad..392be8cf 100644
--- a/src/test/scala/firrtlTests/ParserSpec.scala
+++ b/src/test/scala/firrtlTests/ParserSpec.scala
@@ -117,6 +117,38 @@ class ParserSpec extends FirrtlFlatSpec {
firrtl.Parser.parse(c.serialize)
}
+ // ********** Literal Formats **********
+ "Literals of different bases and signs" should "produce correct values" in {
+ def circuit(lit: String): firrtl.ir.Circuit = {
+ val input = s"""circuit Top :
+ | module lits:
+ | output litout : SInt<16>
+ | litout <= SInt(${lit})
+ |""".stripMargin
+ firrtl.Parser.parse(input)
+ }
+
+ def check(inFormat: String, ref: Integer): Unit = {
+ (circuit(inFormat)) should be (circuit(ref.toString))
+ }
+
+ val checks = Map(
+ """ 12 """ -> 12,
+ """ -14 """ -> -14,
+ """ +15 """ -> 15,
+ """ "hA" """ -> 10,
+ """ "h-C" """ -> -12,
+ """ "h+1B" """ -> 27,
+ """ "o66" """ -> 54,
+ """ "o-33" """ -> -27,
+ """ "b1101" """ -> 13,
+ """ "b-1001" """ -> -9,
+ """ "b+1000" """ -> 8
+ )
+
+ checks.foreach { case (k, v) => check(k, v) }
+ }
+
// ********** Doubles as parameters **********
"Doubles" should "be legal parameters for extmodules" in {
val nums = Seq("1.0", "7.6", "3.00004", "1.0E10", "1.0023E-17")