Add FileInfo to asyncResetAlwaysBlocks (#2451)

* Add FileInfo to asyncResetAlwaysBlocks

Always blocks need three FileInfo (if, true, false) to show line numbers,
but initially, every always blocks only have one FileInfo (false).

RemoveReset adds the extra two FileInfo to sync always blocks,
so sync always blocks can have line numbers.

Async always blocks don't provide their only FileInfo, so there are no line numbers.

This commit gives async always block the extra FileInfo to show line numbers for them.

This code:

```scala
import chisel3._
import chisel3.stage._
import firrtl.CustomDefaultRegisterEmission

class Test extends Module with RequireAsyncReset {
  val io = IO(new Bundle {
    val in = Input(Bool())
    val out = Output(Bool())
  })
  val valid = RegInit(false.B)
  valid := io.in
  io.out := valid
}

object Test extends App {
  new ChiselStage().execute(Array(), Seq(
    ChiselGeneratorAnnotation(() => new Test()),
    CustomDefaultRegisterEmission(useInitAsPreset = false, disableRandomization = true)
  ))
}
```

will generate this Verilog:

```verilog
module Test(
  input   clock,
  input   reset,
  input   io_in,
  output  io_out
);
  reg  valid; // @[Playground.scala 10:22]
  assign io_out = valid; // @[Playground.scala 12:10]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Playground.scala 10:22]
      valid <= 1'h0; // @[Playground.scala 10:22]
    end else begin
      valid <= io_in; // @[Playground.scala 11:9]
    end
  end
endmodule
```

they have correct line numbers (10, 10, 11).

* Add test for async always block line numbers

* Add comment for review

1 files changed, 16 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 4c09c083..1a40cc8f 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -717,6 +717,22 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
     result should containLine("assign z = x == y;")
   }
 
+  it should "show line numbers for AsyncReset regUpdate" in {
+    val result = compileBody(
+      """input clock : Clock
+        |input reset : AsyncReset
+        |output io : { flip in : UInt<1>, out : UInt<1>}
+        |
+        |reg valid : UInt<1>, clock with :
+        |  reset => (reset, UInt<1>("h0")) @[Playground.scala 11:22]
+        |valid <= io.in @[Playground.scala 12:9]
+        |io.out <= valid @[Playground.scala 13:10]""".stripMargin
+    )
+    result should containLine("if (reset) begin // @[Playground.scala 11:22]")
+    result should containLine("valid <= 1'h0; // @[Playground.scala 11:22]")
+    result should containLine("valid <= io_in; // @[Playground.scala 12:9]")
+  }
+
   it should "subtract positive literals instead of adding negative literals" in {
     val compiler = new VerilogCompiler
     val result = compileBody(