diff options
| author | Donggyu | 2016-09-07 17:12:21 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-07 17:12:21 -0700 |
| commit | 303bad7db4354429c1992233fe0bfd1e8ce7f93e (patch) | |
| tree | be6afdc75f2f209f4a412d5aafae5015da98cc2a /src/test | |
| parent | 296a65ebb895d100c3cbde6df7c0303d6942e5d5 (diff) | |
| parent | d7bf6fb7b415d35f967d247119b8975c3dc885a3 (diff) | |
Merge pull request #282 from ucb-bar/refactor_checks
Refactor checks
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/CheckInitializationSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala index 515bbfc8..e2eaf690 100644 --- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala +++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala @@ -60,7 +60,7 @@ class CheckInitializationSpec extends FirrtlFlatSpec { | wire x : UInt<32> | when p : | x <= UInt(1)""".stripMargin - intercept[PassExceptions] { + intercept[CheckInitialization.RefNotInitializedException] { passes.foldLeft(parse(input)) { (c: Circuit, p: Pass) => p.run(c) } @@ -75,7 +75,7 @@ class CheckInitializationSpec extends FirrtlFlatSpec { | when p : | else : | x <= UInt(1)""".stripMargin - intercept[PassExceptions] { + intercept[CheckInitialization.RefNotInitializedException] { passes.foldLeft(parse(input)) { (c: Circuit, p: Pass) => p.run(c) } |
